Device Variation Effects on Neural Network Inference Accuracy in Analog In‐Memory Computing Systems
In analog in‐memory computing systems based on nonvolatile memories such as resistive random‐access memory (RRAM), neural network models are often trained offline and then the weights are programmed onto memory devices as conductance values. The programmed weight values inevitably deviate from the t...
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| Vydané v: | Advanced intelligent systems Ročník 4; číslo 8 |
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Weinheim
John Wiley & Sons, Inc
01.08.2022
Wiley |
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| Abstract | In analog in‐memory computing systems based on nonvolatile memories such as resistive random‐access memory (RRAM), neural network models are often trained offline and then the weights are programmed onto memory devices as conductance values. The programmed weight values inevitably deviate from the target values during the programming process. This effect can be pronounced for emerging memories such as RRAM, PcRAM, and MRAM due to the stochastic nature during programming. Unlike noise, these weight deviations do not change during inference. The performance of neural network models is investigated against this programming variation under realistic system limitations, including limited device on/off ratios, memory array size, analog‐to‐digital converter (ADC) characteristics, and signed weight representations. Approaches to mitigate such device and circuit nonidealities through architecture‐aware training are also evaluated. The effectiveness of variation injection during training to improve the inference robustness, as well as the effects of different neural network training parameters such as learning rate schedule, will be discussed.
In nonvolatile memory‐based analog in‐memory computing systems, variations during device programming can cause neural‐network inference accuracy to degrade since the stored weights will differ from those in the original models. Herein, the performance of deep neural‐network models is investigated against this effect under realistic system limitations, including limited device on/off ratios, memory array size, circuit characteristics, and signed weight representations. |
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| AbstractList | In analog in‐memory computing systems based on nonvolatile memories such as resistive random‐access memory (RRAM), neural network models are often trained offline and then the weights are programmed onto memory devices as conductance values. The programmed weight values inevitably deviate from the target values during the programming process. This effect can be pronounced for emerging memories such as RRAM, PcRAM, and MRAM due to the stochastic nature during programming. Unlike noise, these weight deviations do not change during inference. The performance of neural network models is investigated against this programming variation under realistic system limitations, including limited device on/off ratios, memory array size, analog‐to‐digital converter (ADC) characteristics, and signed weight representations. Approaches to mitigate such device and circuit nonidealities through architecture‐aware training are also evaluated. The effectiveness of variation injection during training to improve the inference robustness, as well as the effects of different neural network training parameters such as learning rate schedule, will be discussed.
In nonvolatile memory‐based analog in‐memory computing systems, variations during device programming can cause neural‐network inference accuracy to degrade since the stored weights will differ from those in the original models. Herein, the performance of deep neural‐network models is investigated against this effect under realistic system limitations, including limited device on/off ratios, memory array size, circuit characteristics, and signed weight representations. In analog in‐memory computing systems based on nonvolatile memories such as resistive random‐access memory (RRAM), neural network models are often trained offline and then the weights are programmed onto memory devices as conductance values. The programmed weight values inevitably deviate from the target values during the programming process. This effect can be pronounced for emerging memories such as RRAM, PcRAM, and MRAM due to the stochastic nature during programming. Unlike noise, these weight deviations do not change during inference. The performance of neural network models is investigated against this programming variation under realistic system limitations, including limited device on/off ratios, memory array size, analog‐to‐digital converter (ADC) characteristics, and signed weight representations. Approaches to mitigate such device and circuit nonidealities through architecture‐aware training are also evaluated. The effectiveness of variation injection during training to improve the inference robustness, as well as the effects of different neural network training parameters such as learning rate schedule, will be discussed. |
| Author | Wang, Qiwen Lu, Wei D. Park, Yongmo |
| Author_xml | – sequence: 1 givenname: Qiwen surname: Wang fullname: Wang, Qiwen organization: University of Michigan – sequence: 2 givenname: Yongmo surname: Park fullname: Park, Yongmo organization: University of Michigan – sequence: 3 givenname: Wei D. orcidid: 0000-0003-4731-1976 surname: Lu fullname: Lu, Wei D. email: wluee@umich.edu organization: University of Michigan |
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| SubjectTerms | Accuracy analog computing Analog to digital converters Arrays Circuits Computation Datasets deep neural networks emerging memory Energy efficiency in-memory computing Inference Internet of Things Memory devices Neural networks process-in-memory Programming RRAM Training Workloads |
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| Title | Device Variation Effects on Neural Network Inference Accuracy in Analog In‐Memory Computing Systems |
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