Scheduling-based power capping in high performance computing systems
•A HPC job dispatcher capable of bounding the power consumption is proposed.•The novel approach combines machine learning techniques and a constraint programming model.•Key idea: predict the power consumption of HPC application and use this knowledge to schedule them effectively.•A thorough comparis...
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| Published in: | Sustainable computing informatics and systems Vol. 19; pp. 1 - 13 |
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| Main Authors: | , , , , |
| Format: | Journal Article |
| Language: | English |
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Elsevier Inc
01.09.2018
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| ISSN: | 2210-5379 |
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| Abstract | •A HPC job dispatcher capable of bounding the power consumption is proposed.•The novel approach combines machine learning techniques and a constraint programming model.•Key idea: predict the power consumption of HPC application and use this knowledge to schedule them effectively.•A thorough comparison with other methods from the state-of-the-art is performed.
Supercomputer installed capacity worldwide increased for many years and further growth is expected in the future. The next goal for high performance computing (HPC) systems is reaching Exascale. The increase in computational power threatens to lead to unacceptable power demands, if future machines will be built using current technology. Therefore reducing supercomputer power consumption has been the subject of intense research. A common approach to curtail the excessive power demands of supercomputers is to hard-bound their consumption, power capping. Power capping can be enforced by reactively throttling system performance when the power bound is hit, or by scheduling workload in a proactive fashion to avoid hitting the bound. In this paper we explore the second approach: our scheduler meets power capping constraints and minimizes quality-of-service (QoS) disruption through smart planning of the job execution order. The approach is based on constraint programming in conjunction with a machine learning module predicting the power consumptions of HPC applications. We evaluate our method on the Eurora supercomputer, using both synthetic workloads and historical traces. Our approach outperforms the state-of-the-art power capping techniques in terms of waiting time and QoS, while keeping schedule computation time under control. |
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| AbstractList | •A HPC job dispatcher capable of bounding the power consumption is proposed.•The novel approach combines machine learning techniques and a constraint programming model.•Key idea: predict the power consumption of HPC application and use this knowledge to schedule them effectively.•A thorough comparison with other methods from the state-of-the-art is performed.
Supercomputer installed capacity worldwide increased for many years and further growth is expected in the future. The next goal for high performance computing (HPC) systems is reaching Exascale. The increase in computational power threatens to lead to unacceptable power demands, if future machines will be built using current technology. Therefore reducing supercomputer power consumption has been the subject of intense research. A common approach to curtail the excessive power demands of supercomputers is to hard-bound their consumption, power capping. Power capping can be enforced by reactively throttling system performance when the power bound is hit, or by scheduling workload in a proactive fashion to avoid hitting the bound. In this paper we explore the second approach: our scheduler meets power capping constraints and minimizes quality-of-service (QoS) disruption through smart planning of the job execution order. The approach is based on constraint programming in conjunction with a machine learning module predicting the power consumptions of HPC applications. We evaluate our method on the Eurora supercomputer, using both synthetic workloads and historical traces. Our approach outperforms the state-of-the-art power capping techniques in terms of waiting time and QoS, while keeping schedule computation time under control. |
| Author | Milano, Michela Borghesi, Andrea Lombardi, Michele Bartolini, Andrea Benini, Luca |
| Author_xml | – sequence: 1 givenname: Andrea surname: Borghesi fullname: Borghesi, Andrea email: andrea.borghesi3@unibo.it organization: DISI, University of Bologna, Viale Risorgimento 2, 40123 Bologna, Italy – sequence: 2 givenname: Andrea surname: Bartolini fullname: Bartolini, Andrea email: barandre@iis.ee.ethz.ch organization: DEI, University of Bologna, Viale Risorgimento 2, 40123 Bologna, Italy – sequence: 3 givenname: Michele surname: Lombardi fullname: Lombardi, Michele email: michele.lombardi2@unibo.it organization: DISI, University of Bologna, Viale Risorgimento 2, 40123 Bologna, Italy – sequence: 4 givenname: Michela surname: Milano fullname: Milano, Michela email: michela.milano@unibo.it organization: DISI, University of Bologna, Viale Risorgimento 2, 40123 Bologna, Italy – sequence: 5 givenname: Luca surname: Benini fullname: Benini, Luca email: luca.benini@iis.ee.ethz.ch organization: DEI, University of Bologna, Viale Risorgimento 2, 40123 Bologna, Italy |
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| Cites_doi | 10.1109/TSUSC.2016.2623775 10.7873/DATE2014.290 10.1109/TPDS.2016.2516997 10.1109/HPCSim.2015.7237023 10.1007/BF00116251 10.1023/A:1010933404324 10.1016/j.parco.2012.08.001 10.1016/j.jpdc.2012.01.006 10.1002/cpe.3191 10.1007/s10586-007-0045-4 10.1016/j.future.2013.12.011 10.1016/j.future.2017.01.015 10.1016/j.future.2015.05.012 10.1016/S1574-6526(06)80026-X 10.1007/s11432-016-5588-7 10.1109/SC.2014.71 10.1007/BF01721162 10.1109/71.932708 10.1109/TPDS.2007.1026 10.1016/j.future.2013.07.012 10.1007/s00450-011-0189-6 10.1007/s00450-010-0129-x |
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| Keywords | Power consumption Constraint programming Machine learning HPC Scheduling Power modeling Optimization |
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| SubjectTerms | Constraint programming HPC Machine learning Optimization Power consumption Power modeling Scheduling |
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