An efficient hardware model for RSA Encryption system using Vedic mathematics
The standard techniques for providing privacy and security in data networks include encryption/decryption algorithms such as Advanced Encryption System (AES) (private-key) and RSA (public-key). RSA is one of the safest standard algorithms, based on public-key, for providing security in networks. Eve...
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| Veröffentlicht in: | Procedia engineering Jg. 30; S. 124 - 128 |
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| Format: | Journal Article |
| Sprache: | Englisch |
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Elsevier Ltd
2012
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| ISSN: | 1877-7058, 1877-7058 |
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| Abstract | The standard techniques for providing privacy and security in data networks include encryption/decryption algorithms such as Advanced Encryption System (AES) (private-key) and RSA (public-key). RSA is one of the safest standard algorithms, based on public-key, for providing security in networks. Even though the RSA Algorithm is an old and simple encryption technique, there is a scope to improve its performance. One of the most time consuming processes in RSA encryption/ decryption algorithm is the computation of ab mod n where “a” is the text, (b, n) is the key. Generally the prime number used for RSA Encryption system will around 100 to 150 decimal digits. The computations involved are tedious and time consuming. Also the hardware is quite complex. To increase the computation speed, the multiplication principle of Vedic mathematics is used and also an improvement is made in the conventional restoring algorithm which does the modulus operation. “Urdhva-tiryakbhyam” is the sutra (principle) which used to compute the multiplication. It literally means vertical and crosswise manipulation. The significance of this technique is that it computes the partial products in one step and avoids the shifting operation which saves both time and hardware. Also an improvement is made in the restoring algorithm by avoiding unnecessary restorations when they are not required. |
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| AbstractList | The standard techniques for providing privacy and security in data networks include encryption/decryption algorithms such as Advanced Encryption System (AES) (private-key) and RSA (public-key). RSA is one of the safest standard algorithms, based on public-key, for providing security in networks. Even though the RSA Algorithm is an old and simple encryption technique, there is a scope to improve its performance. One of the most time consuming processes in RSA encryption/ decryption algorithm is the computation of ab mod n where “a” is the text, (b, n) is the key. Generally the prime number used for RSA Encryption system will around 100 to 150 decimal digits. The computations involved are tedious and time consuming. Also the hardware is quite complex. To increase the computation speed, the multiplication principle of Vedic mathematics is used and also an improvement is made in the conventional restoring algorithm which does the modulus operation. “Urdhva-tiryakbhyam” is the sutra (principle) which used to compute the multiplication. It literally means vertical and crosswise manipulation. The significance of this technique is that it computes the partial products in one step and avoids the shifting operation which saves both time and hardware. Also an improvement is made in the restoring algorithm by avoiding unnecessary restorations when they are not required. |
| Author | Vaya, P.R. Hegde, Ganapathi Bhaskar, R. |
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| Keywords | Vedic mathematics improved restoring algorithm RSA encryption system |
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| References | Nitish Aggarwal, Kartik Asooja (bib0020) 2009 Behrouz A Forouzan, Debdeep Mukhopadhyay,”Cryptography and Network Security”, second edition, Tata McGraw Hill Education Pvt Ltd, 2008. Shamim Akhter (bib0010) 2007 Rivest, Shamir, Adleman (bib0025) 1978; 21 Himanshu Thapliyal, Srinivas (bib0015) 2004 Himanshu Thapliyal and M.B. Srinivas, “VLSI Implementation of RSA Encryption System Using Ancient Indian Vedic Mathematics”, Center for VLSI and Embedded System Technologies, International Institute of Information Technology Hyderabad-500019, India. Sumit Vaidya, Deepak Dandekar (bib0035) 2010 Shamim Akhter (10.1016/j.proeng.2012.01.842_bib0010) 2007 10.1016/j.proeng.2012.01.842_bib0030 Sumit Vaidya (10.1016/j.proeng.2012.01.842_bib0035) 2010 Nitish Aggarwal (10.1016/j.proeng.2012.01.842_bib0020) 2009 Rivest (10.1016/j.proeng.2012.01.842_bib0025) 1978; 21 10.1016/j.proeng.2012.01.842_bib0005 Himanshu Thapliyal (10.1016/j.proeng.2012.01.842_bib0015) 2004 |
| References_xml | – year: 2004 ident: bib0015 article-title: “High speed Efficient Hierarchial Overlay multiplier based on Ancient Indian Vedic mathematics” publication-title: proceedings of International Conference on Signal Processing ICSP 2004, Turkey – volume: 21 start-page: 120 year: 1978 end-page: 126 ident: bib0025 article-title: A Method for Obtaining Digital Signatures and Public-Key Cryptosystems publication-title: Communications of the ACM – reference: Himanshu Thapliyal and M.B. Srinivas, “VLSI Implementation of RSA Encryption System Using Ancient Indian Vedic Mathematics”, Center for VLSI and Embedded System Technologies, International Institute of Information Technology Hyderabad-500019, India. – year: 2010 ident: bib0035 article-title: Delay-Power Performance Comparison of multipliers in VLSI circuit design publication-title: International Journal of Computer Networks & Communications (IJCNC), Vol.2, No.4 – reference: Behrouz A Forouzan, Debdeep Mukhopadhyay,”Cryptography and Network Security”, second edition, Tata McGraw Hill Education Pvt Ltd, 2008. – year: 2009 ident: bib0020 article-title: Saurabh Shekhar Verma, Sapna Negi, An Improvement in the Restoring Division Algorithm publication-title: IEEE – year: 2007 ident: bib0010 article-title: “VHDL Implementation of Fast NXN Multiplier Based on Vedic Mathematics”, Jaypee Institute of Information Technology University, Noida publication-title: 201307 UP, INDIA IEEE – volume: 21 start-page: 120 issue: 2 year: 1978 ident: 10.1016/j.proeng.2012.01.842_bib0025 article-title: A Method for Obtaining Digital Signatures and Public-Key Cryptosystems publication-title: Communications of the ACM doi: 10.1145/359340.359342 – year: 2004 ident: 10.1016/j.proeng.2012.01.842_bib0015 article-title: “High speed Efficient Hierarchial Overlay multiplier based on Ancient Indian Vedic mathematics” publication-title: proceedings of International Conference on Signal Processing ICSP 2004, Turkey – year: 2010 ident: 10.1016/j.proeng.2012.01.842_bib0035 article-title: Delay-Power Performance Comparison of multipliers in VLSI circuit design publication-title: International Journal of Computer Networks & Communications (IJCNC), Vol.2, No.4 – ident: 10.1016/j.proeng.2012.01.842_bib0005 – ident: 10.1016/j.proeng.2012.01.842_bib0030 – year: 2009 ident: 10.1016/j.proeng.2012.01.842_bib0020 article-title: Saurabh Shekhar Verma, Sapna Negi, An Improvement in the Restoring Division Algorithm publication-title: IEEE – year: 2007 ident: 10.1016/j.proeng.2012.01.842_bib0010 article-title: “VHDL Implementation of Fast NXN Multiplier Based on Vedic Mathematics”, Jaypee Institute of Information Technology University, Noida publication-title: 201307 UP, INDIA IEEE |
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| Title | An efficient hardware model for RSA Encryption system using Vedic mathematics |
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