A general hierarchical circuit modeling and simulation algorithm

This paper proposes a new hierarchical circuit modeling and simulation technique in s-domain for linear analog and interconnect circuits. The new method is based on a graph-based symbolic hierarchical circuit decomposition scheme. It can derive the exact or approximate admittances in the reduced cir...

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Vydané v:	IEEE transactions on computer-aided design of integrated circuits and systems Ročník 24; číslo 3; s. 418 - 434
Hlavný autor:	Tan, S.X.-D.
Médium:	Journal Article
Jazyk:	English
Vydavateľské údaje:	New York IEEE 01.03.2005 The Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Predmet:	Admittance Algorithms Behavioral modeling Circuit simulation Computational modeling determinant decision diagrams Frequency Integrated circuit interconnections Matrix decomposition matrix determinant model order reduction Partitioning algorithms Polynomials Power system interconnection Studies System-on-a-chip
ISSN:	0278-0070, 1937-4151
On-line prístup:	Získať plný text
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