A general hierarchical circuit modeling and simulation algorithm

This paper proposes a new hierarchical circuit modeling and simulation technique in s-domain for linear analog and interconnect circuits. The new method is based on a graph-based symbolic hierarchical circuit decomposition scheme. It can derive the exact or approximate admittances in the reduced cir...

Full description

Saved in:

Bibliographic Details
Published in:	IEEE transactions on computer-aided design of integrated circuits and systems Vol. 24; no. 3; pp. 418 - 434
Main Author:	Tan, S.X.-D.
Format:	Journal Article
Language:	English
Published:	New York IEEE 01.03.2005 The Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subjects:	Admittance Algorithms Behavioral modeling Circuit simulation Computational modeling determinant decision diagrams Frequency Integrated circuit interconnections Matrix decomposition matrix determinant model order reduction Partitioning algorithms Polynomials Power system interconnection Studies System-on-a-chip
ISSN:	0278-0070, 1937-4151
Online Access:	Get full text
Tags:	Add Tag No Tags, Be the first to tag this record!

Be the first to leave a comment!