A general hierarchical circuit modeling and simulation algorithm
This paper proposes a new hierarchical circuit modeling and simulation technique in s-domain for linear analog and interconnect circuits. The new method is based on a graph-based symbolic hierarchical circuit decomposition scheme. It can derive the exact or approximate admittances in the reduced cir...
Gespeichert in:
| Veröffentlicht in: | IEEE transactions on computer-aided design of integrated circuits and systems Jg. 24; H. 3; S. 418 - 434 |
|---|---|
| 1. Verfasser: | |
| Format: | Journal Article |
| Sprache: | Englisch |
| Veröffentlicht: |
New York
IEEE
01.03.2005
The Institute of Electrical and Electronics Engineers, Inc. (IEEE) |
| Schlagworte: | |
| ISSN: | 0278-0070, 1937-4151 |
| Online-Zugang: | Volltext |
| Tags: |
Tag hinzufügen
Keine Tags, Fügen Sie den ersten Tag hinzu!
|
| Abstract | This paper proposes a new hierarchical circuit modeling and simulation technique in s-domain for linear analog and interconnect circuits. The new method is based on a graph-based symbolic hierarchical circuit decomposition scheme. It can derive the exact or approximate admittances in the reduced circuit matrix and compute the circuit characteristics in rational function forms for very large linear analog and interconnect circuits. We show that the exact symbolic expressions of a circuit can be obtained by finding the cancellation-free expressions from the same circuit with hierarchical definitions. Some theoretical results are characterized for the presence and conditions of cancellations in the symbolic expressions from the subcircuit reduction. A novel decancellation strategy based on a graph-based hierarchical decomposition process is proposed and canceling terms are removed both symbolically and numerically to obtain the order-reduced circuit models. The proposed method can be used for modeling and simulation of any passive or active linear circuit, which makes our method very attractive for modeling both analog circuits and resistance-capacitance-inductance interconnect circuits in both frequency and time domain. An example RC circuit is illustrated and experimental results with some large analog and interconnects circuits are presented to validate the proposed method. Our experimental results also show that subcircuit (multiple-node) reduction scheme in general is better than one-node reduction methods such as Y-/spl Delta/ transformation in terms of CPU time and memory usage. |
|---|---|
| AbstractList | This paper proposes a new hierarchical circuit modeling and simulation technique in s-domain for linear analog and interconnect circuits. The new method is based on a graph-based symbolic hierarchical circuit decomposition scheme. It can derive the exact or approximate admittances in the reduced circuit matrix and compute the circuit characteristics in rational function forms for very large linear analog and interconnect circuits. We show that the exact symbolic expressions of a circuit can be obtained by finding the cancellation-free expressions from the same circuit with hierarchical definitions. Some theoretical results are characterized for the presence and conditions of cancellations in the symbolic expressions from the subcircuit reduction. A novel decancellation strategy based on a graph-based hierarchical decomposition process is proposed and canceling terms are removed both symbolically and numerically to obtain the order-reduced circuit models. The proposed method can be used for modeling and simulation of any passive or active linear circuit, which makes our method very attractive for modeling both analog circuits and resistance-capacitance-inductance interconnect circuits in both frequency and time domain. An example RC circuit is illustrated and experimental results with some large analog and interconnects circuits are presented to validate the proposed method. Our experimental results also show that subcircuit (multiple-node) reduction scheme in general is better than one-node reduction methods such as Y-/spl Delta/ transformation in terms of CPU time and memory usage. The proposed method can be used for modeling and simulation of any passive or active linear circuit, which makes our method very attractive for modeling both analog circuits and resistance-capacitance-inductance interconnect circuits in both frequency and time domain. |
| Author | Tan, S.X.-D. |
| Author_xml | – sequence: 1 givenname: S.X.-D. surname: Tan fullname: Tan, S.X.-D. organization: Dept. of Electr. Eng., Univ. of California, Riverside, CA, USA |
| BookMark | eNqFkDtPwzAUhS0EEm1hR2KJGNhSrl-1s1GVp1SJpcyW69y0rvIodjLw70kJElIHmM690jn38Y3Jad3USMgVhSmlkN2tFvOHKQMQUy2YpvKEjGjGVSqopKdkBEzpFEDBORnHuAOgQrJsRO7nyQZrDLZMtr6X4Lbe9Y3zwXW-Taomx9LXm8TWeRJ91ZW29U2d2HLTBN9uqwtyVtgy4uWPTsj70-Nq8ZIu355fF_Nl6rhkbco4z5UCDjOZU6aYtrmV60JQB8hyFGta5AqdnSkJfYG0AGpR0rXTthCF5BNyO8zdh-ajw9iaykeHZWlrbLpoWMY0SMH-N2qAGZeiN94cGXdNF-r-CaM1F0zy_ugJgcHkQhNjwMLsg69s-DQUzAG8OYA3B_BmAN9HZkcR59tvam2wvvwreD0EPSL-7uGZ0sD4F9B2kXY |
| CODEN | ITCSDI |
| CitedBy_id | crossref_primary_10_1080_00207721_2022_2037780 crossref_primary_10_1109_TCAD_2024_3416894 crossref_primary_10_1016_j_vlsi_2008_04_006 crossref_primary_10_1109_TVLSI_2012_2197835 crossref_primary_10_1002_cta_2495 crossref_primary_10_1007_s10470_011_9773_8 crossref_primary_10_1016_j_vlsi_2008_06_004 crossref_primary_10_1109_TCAD_2005_850812 crossref_primary_10_1109_TCSII_2008_925655 |
| Cites_doi | 10.1109/ICCAD.2003.159749 10.1109/ICCAD.1996.569710 10.1109/43.384428 10.1109/43.930996 10.1109/ICCAD.2002.1167536 10.1109/TCAD.2003.818303 10.1145/775832.775891 10.1109/TCS.1986.1085914 10.1109/43.980254 10.1109/ICCAD.1999.810649 10.1109/EDTC.1996.494326 10.1109/43.838990 10.1109/43.712097 10.1109/ASPDAC.2003.1195030 10.1109/ICCAD.1996.569707 10.1145/775832.775890 10.1145/775832.776016 10.1109/DATE.2004.1268956 10.1016/S0167-9260(96)00008-9 10.1109/81.382473 10.1109/43.822616 10.1109/5.899053 10.1109/43.45867 10.1109/DAC.1995.249976 10.1145/214392.214398 10.1016/0024-3795(83)80049-4 10.1109/dac.1995.249994 |
| ContentType | Journal Article |
| Copyright | Copyright The Institute of Electrical and Electronics Engineers, Inc. (IEEE) 2005 |
| Copyright_xml | – notice: Copyright The Institute of Electrical and Electronics Engineers, Inc. (IEEE) 2005 |
| DBID | 97E RIA RIE AAYXX CITATION 7SC 7SP 8FD JQ2 L7M L~C L~D 7TB FR3 |
| DOI | 10.1109/TCAD.2004.842815 |
| DatabaseName | IEEE Xplore (IEEE) IEEE All-Society Periodicals Package (ASPP) 1998–Present IEEE Electronic Library (IEL) CrossRef Computer and Information Systems Abstracts Electronics & Communications Abstracts Technology Research Database ProQuest Computer Science Collection Advanced Technologies Database with Aerospace Computer and Information Systems Abstracts Academic Computer and Information Systems Abstracts Professional Mechanical & Transportation Engineering Abstracts Engineering Research Database |
| DatabaseTitle | CrossRef Technology Research Database Computer and Information Systems Abstracts – Academic Electronics & Communications Abstracts ProQuest Computer Science Collection Computer and Information Systems Abstracts Advanced Technologies Database with Aerospace Computer and Information Systems Abstracts Professional Mechanical & Transportation Engineering Abstracts Engineering Research Database |
| DatabaseTitleList | Technology Research Database Technology Research Database Technology Research Database |
| Database_xml | – sequence: 1 dbid: RIE name: IEEE Electronic Library (IEL) url: https://ieeexplore.ieee.org/ sourceTypes: Publisher |
| DeliveryMethod | fulltext_linktorsrc |
| Discipline | Engineering |
| EISSN | 1937-4151 |
| EndPage | 434 |
| ExternalDocumentID | 2425510351 10_1109_TCAD_2004_842815 1397802 |
| Genre | orig-research |
| GroupedDBID | --Z -~X 0R~ 29I 4.4 5GY 5VS 6IK 97E AAJGR AARMG AASAJ AAWTH ABAZT ABQJQ ABVLG ACGFS ACIWK ACNCT AENEX AETIX AGQYO AGSQL AHBIQ AI. AIBXA AKJIK AKQYR ALLEH ALMA_UNASSIGNED_HOLDINGS ASUFR ATWAV BEFXN BFFAM BGNUA BKEBE BPEOZ CS3 DU5 EBS EJD HZ~ H~9 IBMZZ ICLAB IFIPE IFJZH IPLJI JAVBF LAI M43 O9- OCL P2P PZZ RIA RIE RNS TN5 VH1 VJK AAYXX CITATION 7SC 7SP 8FD JQ2 L7M L~C L~D RIG 7TB FR3 |
| ID | FETCH-LOGICAL-c352t-233d7703065d12728ada5bf41c0e2de4b1fd7eca6750d7ee1f01ae51bc8af4f53 |
| IEDL.DBID | RIE |
| ISICitedReferencesCount | 11 |
| ISICitedReferencesURI | http://www.webofscience.com/api/gateway?GWVersion=2&SrcApp=Summon&SrcAuth=ProQuest&DestLinkType=CitingArticles&DestApp=WOS_CPL&KeyUT=000227261300009&url=https%3A%2F%2Fcvtisr.summon.serialssolutions.com%2F%23%21%2Fsearch%3Fho%3Df%26include.ft.matches%3Dt%26l%3Dnull%26q%3D |
| ISSN | 0278-0070 |
| IngestDate | Sun Sep 28 04:23:36 EDT 2025 Sat Sep 27 23:44:55 EDT 2025 Mon Jun 30 10:23:09 EDT 2025 Tue Nov 18 20:57:53 EST 2025 Sat Nov 29 08:06:06 EST 2025 Tue Aug 26 16:40:10 EDT 2025 |
| IsPeerReviewed | true |
| IsScholarly | true |
| Issue | 3 |
| Language | English |
| License | https://ieeexplore.ieee.org/Xplorehelp/downloads/license-information/IEEE.html |
| LinkModel | DirectLink |
| MergedId | FETCHMERGED-LOGICAL-c352t-233d7703065d12728ada5bf41c0e2de4b1fd7eca6750d7ee1f01ae51bc8af4f53 |
| Notes | ObjectType-Article-2 SourceType-Scholarly Journals-1 ObjectType-Feature-1 content type line 14 content type line 23 |
| PQID | 883425323 |
| PQPubID | 23500 |
| PageCount | 17 |
| ParticipantIDs | ieee_primary_1397802 proquest_journals_883425323 crossref_citationtrail_10_1109_TCAD_2004_842815 crossref_primary_10_1109_TCAD_2004_842815 proquest_miscellaneous_29280542 proquest_miscellaneous_28006354 |
| PublicationCentury | 2000 |
| PublicationDate | 2005-March 2005-03-00 20050301 |
| PublicationDateYYYYMMDD | 2005-03-01 |
| PublicationDate_xml | – month: 03 year: 2005 text: 2005-March |
| PublicationDecade | 2000 |
| PublicationPlace | New York |
| PublicationPlace_xml | – name: New York |
| PublicationTitle | IEEE transactions on computer-aided design of integrated circuits and systems |
| PublicationTitleAbbrev | TCAD |
| PublicationYear | 2005 |
| Publisher | IEEE The Institute of Electrical and Electronics Engineers, Inc. (IEEE) |
| Publisher_xml | – name: IEEE – name: The Institute of Electrical and Electronics Engineers, Inc. (IEEE) |
| References | ref13 ref35 ref15 ref37 ref14 Gantmacher (ref8) 1977; 1 ref11 ref10 Yang (ref32) ref2 ref1 ref16 ref19 Vlach (ref31) 1995 ref18 Yu (ref36) 2004 Pillage (ref17) 1994 Yang (ref33) ref24 ref23 ref26 ref25 ref20 ref22 ref21 Tan (ref30) 2000; 19 Tan (ref28) 2003; E86-A ref27 ref7 ref9 Tan (ref29) ref4 ref3 ref6 ref5 Yang (ref34) Lillis (ref12) 1999 |
| References_xml | – ident: ref26 doi: 10.1109/ICCAD.2003.159749 – ident: ref23 doi: 10.1109/ICCAD.1996.569710 – volume-title: Interconnect Analysis and Synthesis year: 1999 ident: ref12 – volume: 1 volume-title: The Theory of Matrices year: 1977 ident: ref8 – ident: ref5 doi: 10.1109/43.384428 – ident: ref22 doi: 10.1109/43.930996 – ident: ref15 doi: 10.1109/ICCAD.2002.1167536 – ident: ref37 doi: 10.1109/TCAD.2003.818303 – ident: ref1 doi: 10.1145/775832.775891 – start-page: 222 volume-title: Proc. Int. Conf. Computer-Aided Design ident: ref34 article-title: Hurwitz stable reduced order modeling for RLC interconnect trees – ident: ref25 doi: 10.1109/TCS.1986.1085914 – ident: ref11 doi: 10.1109/43.980254 – ident: ref20 doi: 10.1109/ICCAD.1999.810649 – ident: ref4 doi: 10.1109/EDTC.1996.494326 – volume: 19 start-page: 401 issue: 4 year: 2000 ident: ref30 article-title: Hierarchical symbolic analysis of large analog circuits via determinant decision diagrams publication-title: IEEE Trans. Computer-Aided Design Integr. Circuits Syst. doi: 10.1109/43.838990 – ident: ref14 doi: 10.1109/43.712097 – ident: ref18 doi: 10.1109/ASPDAC.2003.1195030 – ident: ref7 doi: 10.1109/ICCAD.1996.569707 – ident: ref19 doi: 10.1145/775832.775890 – ident: ref35 doi: 10.1145/775832.776016 – ident: ref27 doi: 10.1109/DATE.2004.1268956 – ident: ref3 doi: 10.1016/S0167-9260(96)00008-9 – ident: ref10 doi: 10.1109/81.382473 – ident: ref21 doi: 10.1109/43.822616 – ident: ref9 doi: 10.1109/5.899053 – ident: ref16 doi: 10.1109/43.45867 – ident: ref24 doi: 10.1109/DAC.1995.249976 – start-page: V105 volume-title: Proc. IEEE Int. Symp. Circuits Syst. ident: ref32 article-title: Behavioral modeling of analog circuits by dynamic semisymbolic analysis – start-page: 239 volume-title: Proc. IEEE Int. System-on-Chip Conf. ident: ref29 article-title: Hurwitz stable model reduction for nontree structured RLCK circuits – ident: ref13 doi: 10.1145/214392.214398 – ident: ref2 doi: 10.1016/0024-3795(83)80049-4 – ident: ref6 doi: 10.1109/dac.1995.249994 – start-page: V129 volume-title: Proc. IEEE Int. Symp. Circuits Syst. ident: ref33 article-title: An efficient algorithm for transient and distortion analysis of mildly nonlinear analog circuits – volume: E86-A start-page: 3112 issue: 12 year: 2003 ident: ref28 article-title: Efficient DDD-based interpretable symbolic characterization of large analog circuits publication-title: IEICE Trans. Fundam. Electron., Commun. Comput. Sci. – volume-title: Computer Methods for Circuit Analysis and Design year: 1995 ident: ref31 – volume-title: Electronic Circuit and System Simulation Methods year: 1994 ident: ref17 – volume-title: rVPEC: Realizable Model for RLCM Network Based on Hierachical Circuit Reduction year: 2004 ident: ref36 |
| SSID | ssj0014529 |
| Score | 1.8010358 |
| Snippet | This paper proposes a new hierarchical circuit modeling and simulation technique in s-domain for linear analog and interconnect circuits. The new method is... The proposed method can be used for modeling and simulation of any passive or active linear circuit, which makes our method very attractive for modeling both... |
| SourceID | proquest crossref ieee |
| SourceType | Aggregation Database Enrichment Source Index Database Publisher |
| StartPage | 418 |
| SubjectTerms | Admittance Algorithms Behavioral modeling Circuit simulation Computational modeling determinant decision diagrams Frequency Integrated circuit interconnections Matrix decomposition matrix determinant model order reduction Partitioning algorithms Polynomials Power system interconnection Studies System-on-a-chip |
| Title | A general hierarchical circuit modeling and simulation algorithm |
| URI | https://ieeexplore.ieee.org/document/1397802 https://www.proquest.com/docview/883425323 https://www.proquest.com/docview/28006354 https://www.proquest.com/docview/29280542 |
| Volume | 24 |
| WOSCitedRecordID | wos000227261300009&url=https%3A%2F%2Fcvtisr.summon.serialssolutions.com%2F%23%21%2Fsearch%3Fho%3Df%26include.ft.matches%3Dt%26l%3Dnull%26q%3D |
| hasFullText | 1 |
| inHoldings | 1 |
| isFullTextHit | |
| isPrint | |
| journalDatabaseRights | – providerCode: PRVIEE databaseName: IEEE Electronic Library (IEL) customDbUrl: eissn: 1937-4151 dateEnd: 99991231 omitProxy: false ssIdentifier: ssj0014529 issn: 0278-0070 databaseCode: RIE dateStart: 19820101 isFulltext: true titleUrlDefault: https://ieeexplore.ieee.org/ providerName: IEEE |
| link | http://cvtisr.summon.serialssolutions.com/2.0.0/link/0/eLvHCXMwlV1LS8NAEB6qeNCDryrW5x68CKbNY7e7uSmieJDiQcFb2OyjBjSRNvX3u7NJq6AUvAUyIcnMPmb22_0-gHOWa8VCibA6GwbUZaSBkDwN7FBry3JLufSRfuCjkXh5SR87cLk4C2OM8ZvPTB8vPZavKzXDpbIBZisCmSNXOB82Z7UWiAECiH49BRljXTueQ5JhOnhyP-Urwb5wyTYK4P6Ygrymyq-B2M8ud1v_-65t2GyzSHLdhH0HOqbchY0f3IJduLom44ZSmqDctQcMXDyIKiZqVtTES-A4SyJLTabFeyvjReTbuJoU9ev7Hjzf3T7d3AetXEKgXBZVB3GSaI4deMh0FPNYSC3R25EKTawNzSOruVHSlQihuzCRDSNpWJQrIS21LNmH1bIqzQGQhEplmHTljeBUWJ1SpYx1yQRjNjFx2oPB3IOZarnEUdLiLfM1RZhm6HOUuKRZ4_MeXCye-Gh4NJbYdtHH33aNe3twNA9S1na0aSZE4kadJE56cLa463oIwh6yNNVsmsUC8zBGl1ikzobR-PDvFx_Buids9TvPjmG1nszMCaypz7qYTk59M_wC6kra7g |
| linkProvider | IEEE |
| linkToHtml | http://cvtisr.summon.serialssolutions.com/2.0.0/link/0/eLvHCXMwlV1LS8NAEB6KCurBt1jrYw9eBGPz2G02N0UsFWvxUMFb2O6jBtpU2tTf784mrYIieAtkQpKZfczst_t9ABdsoCTzBcLqrOVRm5F6XMSJZ1pKGTYwNBYu0t241-Ovr8lzDa6WZ2G01m7zmb7GS4flq4mc41JZE7MVjsyRq6icxcrTWkvMACFEt6KCnLG2JS9AST9p9u1vuVrwmtt0GyVwv01CTlXlx1Ds5pf29v--bAe2qjyS3JaB34Wazvdg8xu74D7c3JJhSSpNUPDaQQY2IkRmUznPCuJEcKwlEbkis2xcCXkRMRpOplnxNj6Al_Z9_67jVYIJnrR5VOGFUaRi7MItpoIwDrlQAv0dSF-HStNBYFSspbBFgm8vdGD8QGgWDCQXhhoWHcJKPsn1EZCICqmZsAUOjyk3KqFSamPTCcZMpMOkDs2FB1NZsYmjqMUodVWFn6TocxS5pGnp8zpcLp94L5k0_rDdRx9_2ZXurUNjEaS06mqzlPPIjjtRGNXhfHnX9hEEPkSuJ_NZGnLMxBj9wyKxNoyGx7-_-BzWO_2nbtp96D02YMPRt7p9aCewUkzn-hTW5EeRzaZnrkl-An4e3jk |
| openUrl | ctx_ver=Z39.88-2004&ctx_enc=info%3Aofi%2Fenc%3AUTF-8&rfr_id=info%3Asid%2Fsummon.serialssolutions.com&rft_val_fmt=info%3Aofi%2Ffmt%3Akev%3Amtx%3Ajournal&rft.genre=article&rft.atitle=A+general+hierarchical+circuit+modeling+and+simulation+algorithm&rft.jtitle=IEEE+transactions+on+computer-aided+design+of+integrated+circuits+and+systems&rft.au=Tan%2C+S+X-D&rft.date=2005-03-01&rft.issn=0278-0070&rft.volume=24&rft.issue=3&rft.spage=418&rft.epage=434&rft_id=info:doi/10.1109%2FTCAD.2004.842815&rft.externalDBID=NO_FULL_TEXT |
| thumbnail_l | http://covers-cdn.summon.serialssolutions.com/index.aspx?isbn=/lc.gif&issn=0278-0070&client=summon |
| thumbnail_m | http://covers-cdn.summon.serialssolutions.com/index.aspx?isbn=/mc.gif&issn=0278-0070&client=summon |
| thumbnail_s | http://covers-cdn.summon.serialssolutions.com/index.aspx?isbn=/sc.gif&issn=0278-0070&client=summon |