High-level dataflow programming for real-time image processing on smart cameras
We describe the application of the caph programming language to the implementation of complex real-time image processing application on a FPGA embedded in a smart camera architecture. caph is based upon the dataflow model of computation. Applications are described as networks of purely dataflow acto...
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| Veröffentlicht in: | Journal of real-time image processing Jg. 12; H. 4; S. 635 - 647 |
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| Format: | Journal Article |
| Sprache: | Englisch |
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Berlin/Heidelberg
Springer Berlin Heidelberg
01.12.2016
Springer Nature B.V Springer Verlag |
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| ISSN: | 1861-8200, 1861-8219 |
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| Abstract | We describe the application of the
caph
programming language to the implementation of complex real-time image processing application on a FPGA embedded in a smart camera architecture.
caph
is based upon the dataflow model of computation. Applications are described as networks of purely dataflow actors exchanging tokens through unidirectional channels and the behavior of each actor is defined as a set of transition rules using pattern matching. We show that this model is naturally suited to the description of applications operating on the fly on digital video streams and supports a fully automated compilation path producing efficient VHDL code. This is demonstrated on an application performing the extraction of HOG (histogram of oriented gradient) feature vectors in real time on the
dreamcam
smart camera, an experimental platform developed at our institute. |
|---|---|
| AbstractList | We describe the application of the
caph
programming language to the implementation of complex real-time image processing application on a FPGA embedded in a smart camera architecture.
caph
is based upon the dataflow model of computation. Applications are described as networks of purely dataflow actors exchanging tokens through unidirectional channels and the behavior of each actor is defined as a set of transition rules using pattern matching. We show that this model is naturally suited to the description of applications operating on the fly on digital video streams and supports a fully automated compilation path producing efficient VHDL code. This is demonstrated on an application performing the extraction of HOG (histogram of oriented gradient) feature vectors in real time on the
dreamcam
smart camera, an experimental platform developed at our institute. We describe the application of the caph programming language to the implementation of complex real-time image processing application on a FPGA embedded in a smart camera architecture. caph is based upon the dataflow model of computation. Applications are described as networks of purely dataflow actors exchanging tokens through unidirectional channels and the behavior of each actor is defined as a set of transition rules using pattern matching. We show that this model is naturally suited to the description of applications operating on the fly on digital video streams and supports a fully automated compilation path producing efficient VHDL code. This is demonstrated on an application performing the extraction of HOG (histogram of oriented gradient) feature vectors in real time on the dreamcam smart camera, an experimental platform developed at our institute. |
| Author | Sérot, Jocelyn Berry, François Bourrasset, Cédric |
| Author_xml | – sequence: 1 givenname: Jocelyn surname: Sérot fullname: Sérot, Jocelyn email: Jocelyn.Serot@univ-bpclermont.fr organization: Institut Pascal, Université Blaise Pascal/CNRS – sequence: 2 givenname: François surname: Berry fullname: Berry, François organization: Institut Pascal, Université Blaise Pascal/CNRS – sequence: 3 givenname: Cédric surname: Bourrasset fullname: Bourrasset, Cédric organization: Institut Pascal, Université Blaise Pascal/CNRS |
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| CitedBy_id | crossref_primary_10_1109_LES_2017_2743247 crossref_primary_10_1016_j_micpro_2020_103326 crossref_primary_10_1109_TCAD_2018_2834439 crossref_primary_10_1007_s11265_018_1351_1 crossref_primary_10_1007_s11554_018_0836_2 |
| Cites_doi | 10.1109/IIH-MSP.2009.216 10.1109/CVPR.2005.177 10.1145/1543820.1543829 10.1109/MC.2003.1220583 10.1109/DICTA.2008.37 10.1016/j.sysarc.2014.01.006 10.1109/CVPRW.2010.5543772 10.1016/S0167-8191(99)00070-8 10.1109/CVPR.2009.5206631 10.1145/360276.360326 10.1109/ICVD.2003.1183177 10.1109/CVPR.2006.119 10.1109/TPAMI.2008.260 10.1109/FPL.2011.32 |
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| Copyright | Springer-Verlag Berlin Heidelberg 2014 Springer-Verlag Berlin Heidelberg 2014. Distributed under a Creative Commons Attribution 4.0 International License |
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| Keywords | HOG Real-time image processing DSL FPGA Dataflow |
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| References | Bauer, S., Kohler, S., Doll, K., Brunsmann, U.: Fpga-gpu architecture for kernel svm pedestrian detection. In: 2010 IEEE Computer Society Conference on, Computer Vision and Pattern Recognition Workshops (CVPRW), pp. 61–68 (2010) Handel-c language reference manual (2009). http://www.agilityds.com/literature/HandelC_Language_Reference_Manual Ahmed, S.: Application of a Dataflow Programming Language to the High Level Synthesis of Real-Time Vision Systems on Reconfigurable Hardware. PhD thesis, Université Blaise Pascal-Clermont-Ferrand II, (2013) Lucarz, C., Mattavelli, M., Wipliez, M., Roquier, G., Raulet, M., Janneck, J., Miller, I., Parlour, D.: Dataflow/Actor-Oriented language for the design of complex signal processing systems. In: Proceedings of the 2008 Conference on Design and Architectures for Signal and Image Processing, DASIP 2008, pp. 168–175 (2008) Frigo, J., Gokhale, M., Lavenier, D.: Evaluation of the streams-C C-to-FPGA compiler: an applications perspective. In: Proceedings of the 2001 ACM/SIGDA ninth international symposium on Field programmable gate arrays, FPGA ’01, pp. 134–140. ACM, New York, NY (2001). doi:10.1145/360276.360326 NajjarWABoehmWDraperBAHammesJRinkerRBeveridgeJRChawatheMRossCHigh-level language abstraction for reconfigurable computingComputer200336636910.1109/MC.2003.1220583 Dahlin, A., Ersfolk, J., Yang, G., Habli, H., Lilius, J.: The Canals language and its compiler. In: Proceedings of th 12th International Workshop on Software and Compilers for Embedded Systems, SCOPES ’09, ACM, pp. 43–52. New York, NY, USA (2009) Enzweiler, M., Gavrila, D.M.: Monocular Pedestrian Detection: Survey and Experiments. In: IEEE Transactions on Pattern Analysis and Machine Intelligence (PAMI), (2008) Kadota, R., Sugano, H., Hiromoto, M., Ochi, H., Miyamoto, R., Nakamura, Y.: Hardware architecture for hog feature extraction. In: Proceedings of the 2009 Fifth International Conference on Intelligent Information Hiding and Multimedia Signal Processing, IEEE Computer Society, pp. 1330–1333. Washington, DC, USA (2009) Zhu, Q., Yeh, M.-C., Cheng, K.-T., Avidan, S.: Fast human detection using a cascade of histograms of oriented gradients. In: Proceedings of the 2006 IEEE Computer Society Conference on Computer Vision and Pattern Recognition, IEEE Computer Society, vol 2, pp. 1491–1498. Washington, DC, USA (2006) Impulse accelerated technologies. http://www.impulsec.com Dollr, P., Wojek, C., Schiele, B., Perona, P.: Pedestrian detection: A benchmark. In: IEEE International Conference on Computer Vision and Pattern Recognition (CVPR), (2009) Birem, M., Berry, F.: DreamCam: a modular FPGA-based smart camera architecture. J. Syst. Archit. 60(6), 519–527 (2014). doi:10.1016/j.sysarc.2014.01.006 Gupta, S., Dutt, N., Gupta, R., Nicolau, A.: Spark A high-level synthesis framework for applying parallelizing compiler transformations. In: International Conference on VLSI Design, pp. 461–466 (2003) Sérot, J.: The semantics of a purely functional graph notation system. In: Achten, P., Koopman, P.W.M., Morazán, M.T. (eds.) Draft Proceedings of the Ninth Symposium on Trends in Functional Programming, TFP 2008, May 26–28. Nijmegen, The Netherlands (2008) Sérot, J., Berry, F., Ahmed, S.: Implementing stream-processing applications on fpgas: a dsl-based approach. In: Proceedings of the 2011 21st International Conference on Field Programmable Logic and Applications, FPL ’11, IEEE Computer Society, pp. 130–137. Washington, DC, USA (2011) Cao, P., Deng, G.: Real-time vision- based stop sign detection system on FPGA. In: International Conference on Digital Image Computing: Techniques and Applications (DICTA), IEEE Computer Society, pp. 465–471 (2008) SérotJBerryFAhmedSAthanasPCAPH: a language for implementing stream-processing applications on FPGAsEmbedded Systems Design with FPGAs2013New YorkSpringer Dalal, N., Triggs, B.: Histograms of oriented gradients for human detection. In: Schmid, C., Soatto, S., Tomasi, C. (eds) International Conference on Computer Vision and Pattern Recognition, vol. 2, pp. 886–893. June (2005) Sérot, J.: The caph software and reference manual. http://caph.univ-bpclermont.fr NajjarWALeeEAGaoGRAdvances in the dataflow computational modelParallel Comput.19992513–141907192910.1016/S0167-8191(99)00070-8 462_CR4 462_CR5 462_CR2 462_CR3 462_CR11 462_CR1 462_CR12 462_CR20 462_CR10 462_CR21 462_CR8 462_CR9 462_CR6 462_CR7 WA Najjar (462_CR14) 1999; 25 J Sérot (462_CR18) 2013 462_CR16 462_CR13 462_CR19 WA Najjar (462_CR15) 2003; 36 462_CR17 |
| References_xml | – reference: Gupta, S., Dutt, N., Gupta, R., Nicolau, A.: Spark A high-level synthesis framework for applying parallelizing compiler transformations. In: International Conference on VLSI Design, pp. 461–466 (2003) – reference: Ahmed, S.: Application of a Dataflow Programming Language to the High Level Synthesis of Real-Time Vision Systems on Reconfigurable Hardware. PhD thesis, Université Blaise Pascal-Clermont-Ferrand II, (2013) – reference: Cao, P., Deng, G.: Real-time vision- based stop sign detection system on FPGA. In: International Conference on Digital Image Computing: Techniques and Applications (DICTA), IEEE Computer Society, pp. 465–471 (2008) – reference: Handel-c language reference manual (2009). http://www.agilityds.com/literature/HandelC_Language_Reference_Manual – reference: Sérot, J.: The caph software and reference manual. http://caph.univ-bpclermont.fr – reference: SérotJBerryFAhmedSAthanasPCAPH: a language for implementing stream-processing applications on FPGAsEmbedded Systems Design with FPGAs2013New YorkSpringer – reference: Birem, M., Berry, F.: DreamCam: a modular FPGA-based smart camera architecture. J. Syst. Archit. 60(6), 519–527 (2014). doi:10.1016/j.sysarc.2014.01.006 – reference: Impulse accelerated technologies. http://www.impulsec.com – reference: Lucarz, C., Mattavelli, M., Wipliez, M., Roquier, G., Raulet, M., Janneck, J., Miller, I., Parlour, D.: Dataflow/Actor-Oriented language for the design of complex signal processing systems. In: Proceedings of the 2008 Conference on Design and Architectures for Signal and Image Processing, DASIP 2008, pp. 168–175 (2008) – reference: Dalal, N., Triggs, B.: Histograms of oriented gradients for human detection. In: Schmid, C., Soatto, S., Tomasi, C. (eds) International Conference on Computer Vision and Pattern Recognition, vol. 2, pp. 886–893. June (2005) – reference: Dollr, P., Wojek, C., Schiele, B., Perona, P.: Pedestrian detection: A benchmark. In: IEEE International Conference on Computer Vision and Pattern Recognition (CVPR), (2009) – reference: Dahlin, A., Ersfolk, J., Yang, G., Habli, H., Lilius, J.: The Canals language and its compiler. In: Proceedings of th 12th International Workshop on Software and Compilers for Embedded Systems, SCOPES ’09, ACM, pp. 43–52. New York, NY, USA (2009) – reference: Kadota, R., Sugano, H., Hiromoto, M., Ochi, H., Miyamoto, R., Nakamura, Y.: Hardware architecture for hog feature extraction. In: Proceedings of the 2009 Fifth International Conference on Intelligent Information Hiding and Multimedia Signal Processing, IEEE Computer Society, pp. 1330–1333. Washington, DC, USA (2009) – reference: NajjarWABoehmWDraperBAHammesJRinkerRBeveridgeJRChawatheMRossCHigh-level language abstraction for reconfigurable computingComputer200336636910.1109/MC.2003.1220583 – reference: Enzweiler, M., Gavrila, D.M.: Monocular Pedestrian Detection: Survey and Experiments. In: IEEE Transactions on Pattern Analysis and Machine Intelligence (PAMI), (2008) – reference: Zhu, Q., Yeh, M.-C., Cheng, K.-T., Avidan, S.: Fast human detection using a cascade of histograms of oriented gradients. In: Proceedings of the 2006 IEEE Computer Society Conference on Computer Vision and Pattern Recognition, IEEE Computer Society, vol 2, pp. 1491–1498. Washington, DC, USA (2006) – reference: Sérot, J., Berry, F., Ahmed, S.: Implementing stream-processing applications on fpgas: a dsl-based approach. In: Proceedings of the 2011 21st International Conference on Field Programmable Logic and Applications, FPL ’11, IEEE Computer Society, pp. 130–137. Washington, DC, USA (2011) – reference: Frigo, J., Gokhale, M., Lavenier, D.: Evaluation of the streams-C C-to-FPGA compiler: an applications perspective. In: Proceedings of the 2001 ACM/SIGDA ninth international symposium on Field programmable gate arrays, FPGA ’01, pp. 134–140. ACM, New York, NY (2001). doi:10.1145/360276.360326 – reference: Bauer, S., Kohler, S., Doll, K., Brunsmann, U.: Fpga-gpu architecture for kernel svm pedestrian detection. In: 2010 IEEE Computer Society Conference on, Computer Vision and Pattern Recognition Workshops (CVPRW), pp. 61–68 (2010) – reference: NajjarWALeeEAGaoGRAdvances in the dataflow computational modelParallel Comput.19992513–141907192910.1016/S0167-8191(99)00070-8 – reference: Sérot, J.: The semantics of a purely functional graph notation system. In: Achten, P., Koopman, P.W.M., Morazán, M.T. (eds.) Draft Proceedings of the Ninth Symposium on Trends in Functional Programming, TFP 2008, May 26–28. Nijmegen, The Netherlands (2008) – ident: 462_CR21 – volume-title: Embedded Systems Design with FPGAs year: 2013 ident: 462_CR18 – ident: 462_CR4 – ident: 462_CR12 doi: 10.1109/IIH-MSP.2009.216 – ident: 462_CR6 doi: 10.1109/CVPR.2005.177 – ident: 462_CR7 doi: 10.1145/1543820.1543829 – ident: 462_CR13 – volume: 36 start-page: 63 year: 2003 ident: 462_CR15 publication-title: Computer doi: 10.1109/MC.2003.1220583 – ident: 462_CR16 – ident: 462_CR5 doi: 10.1109/DICTA.2008.37 – ident: 462_CR3 doi: 10.1016/j.sysarc.2014.01.006 – ident: 462_CR2 doi: 10.1109/CVPRW.2010.5543772 – volume: 25 start-page: 1907 issue: 13–14 year: 1999 ident: 462_CR14 publication-title: Parallel Comput. doi: 10.1016/S0167-8191(99)00070-8 – ident: 462_CR8 doi: 10.1109/CVPR.2009.5206631 – ident: 462_CR10 doi: 10.1145/360276.360326 – ident: 462_CR11 doi: 10.1109/ICVD.2003.1183177 – ident: 462_CR1 – ident: 462_CR19 doi: 10.1109/CVPR.2006.119 – ident: 462_CR9 doi: 10.1109/TPAMI.2008.260 – ident: 462_CR20 – ident: 462_CR17 doi: 10.1109/FPL.2011.32 |
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caph
programming language to the implementation of complex real-time image processing application on a FPGA embedded in a... We describe the application of the caph programming language to the implementation of complex real-time image processing application on a FPGA embedded in a... |
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| SubjectTerms | Cameras Computer Graphics Computer Science Computer Vision and Pattern Recognition Design Hardware Architecture Image processing Image Processing and Computer Vision Language Multimedia Information Systems Pattern matching Pattern Recognition Programmers Programming languages Real-time programming Semantics Signal processing Signal,Image and Speech Processing Special Issue Paper Transition rules Video data |
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| Title | High-level dataflow programming for real-time image processing on smart cameras |
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