In‐Memory Computing with Memristor Content Addressable Memories for Pattern Matching

The dramatic rise of data‐intensive workloads has revived application‐specific computational hardware for continuing speed and power improvements, frequently achieved by limiting data movement and implementing “in‐memory computation”. However, conventional complementary metal oxide semiconductor (CM...

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Published in:	Advanced materials (Weinheim) Vol. 32; no. 37; pp. e2003437 - n/a
Main Authors:	Graves, Catherine E., Li, Can, Sheng, Xia, Miller, Darrin, Ignowski, Jim, Kiyama, Lennie, Strachan, John Paul
Format:	Journal Article
Language:	English
Published:	Weinheim Wiley Subscription Services, Inc 01.09.2020
Subjects:	Arrays Associative memory Automata theory Circuit design CMOS Computation content addressable memory Finite state machines in‐memory computing Mapping Materials science Memristors Pattern matching Power efficiency Power management Random access memory Resistance
ISSN:	0935-9648, 1521-4095, 1521-4095
Online Access:	Get full text
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Abstract	The dramatic rise of data‐intensive workloads has revived application‐specific computational hardware for continuing speed and power improvements, frequently achieved by limiting data movement and implementing “in‐memory computation”. However, conventional complementary metal oxide semiconductor (CMOS) circuit designs can still suffer low power efficiency, motivating designs leveraging nonvolatile resistive random access memory (ReRAM), and with many studies focusing on crossbar circuit architectures. Another circuit primitive—content addressable memory (CAM)—shows great promise for mapping a diverse range of computational models for in‐memory computation, with recent ReRAM–CAM designs proposed but few experimentally demonstrated. Here, programming and control of memristors across an 86 × 12 memristor ternary CAM (TCAM) array integrated with CMOS are demonstrated, and parameter tradeoffs for optimizing speed and search margin are evaluated. In addition to smaller area, this memristor TCAM results in significantly lower power due to very low programmable conductance states, motivating CAM use in a wider range of computational applications than conventional TCAMs are confined to today. Finally, the first experimental demonstration of two computational models in memristor TCAM arrays is reported: regular expression matching in a finite state machine for network security intrusion detection and definable inexact pattern matching in a Levenshtein automata for genomic sequencing. Memristor content addressable memory (CAM) arrays with nanoscale memristor devices are developed experimentally and used to demonstrate two novel computing applications on‐chip—network security intrusion detection using a finite state machine and definable inexact pattern matching in a Levenshtein automata for genomic sequencing. This work demonstrates the promise of in‐memory compute circuits using emerging devices to accelerate broad computing applications.
AbstractList	The dramatic rise of data‐intensive workloads has revived application‐specific computational hardware for continuing speed and power improvements, frequently achieved by limiting data movement and implementing “in‐memory computation”. However, conventional complementary metal oxide semiconductor (CMOS) circuit designs can still suffer low power efficiency, motivating designs leveraging nonvolatile resistive random access memory (ReRAM), and with many studies focusing on crossbar circuit architectures. Another circuit primitive—content addressable memory (CAM)—shows great promise for mapping a diverse range of computational models for in‐memory computation, with recent ReRAM–CAM designs proposed but few experimentally demonstrated. Here, programming and control of memristors across an 86 × 12 memristor ternary CAM (TCAM) array integrated with CMOS are demonstrated, and parameter tradeoffs for optimizing speed and search margin are evaluated. In addition to smaller area, this memristor TCAM results in significantly lower power due to very low programmable conductance states, motivating CAM use in a wider range of computational applications than conventional TCAMs are confined to today. Finally, the first experimental demonstration of two computational models in memristor TCAM arrays is reported: regular expression matching in a finite state machine for network security intrusion detection and definable inexact pattern matching in a Levenshtein automata for genomic sequencing. The dramatic rise of data‐intensive workloads has revived application‐specific computational hardware for continuing speed and power improvements, frequently achieved by limiting data movement and implementing “in‐memory computation”. However, conventional complementary metal oxide semiconductor (CMOS) circuit designs can still suffer low power efficiency, motivating designs leveraging nonvolatile resistive random access memory (ReRAM), and with many studies focusing on crossbar circuit architectures. Another circuit primitive—content addressable memory (CAM)—shows great promise for mapping a diverse range of computational models for in‐memory computation, with recent ReRAM–CAM designs proposed but few experimentally demonstrated. Here, programming and control of memristors across an 86 × 12 memristor ternary CAM (TCAM) array integrated with CMOS are demonstrated, and parameter tradeoffs for optimizing speed and search margin are evaluated. In addition to smaller area, this memristor TCAM results in significantly lower power due to very low programmable conductance states, motivating CAM use in a wider range of computational applications than conventional TCAMs are confined to today. Finally, the first experimental demonstration of two computational models in memristor TCAM arrays is reported: regular expression matching in a finite state machine for network security intrusion detection and definable inexact pattern matching in a Levenshtein automata for genomic sequencing. Memristor content addressable memory (CAM) arrays with nanoscale memristor devices are developed experimentally and used to demonstrate two novel computing applications on‐chip—network security intrusion detection using a finite state machine and definable inexact pattern matching in a Levenshtein automata for genomic sequencing. This work demonstrates the promise of in‐memory compute circuits using emerging devices to accelerate broad computing applications. The dramatic rise of data-intensive workloads has revived application-specific computational hardware for continuing speed and power improvements, frequently achieved by limiting data movement and implementing "in-memory computation". However, conventional complementary metal oxide semiconductor (CMOS) circuit designs can still suffer low power efficiency, motivating designs leveraging nonvolatile resistive random access memory (ReRAM), and with many studies focusing on crossbar circuit architectures. Another circuit primitive-content addressable memory (CAM)-shows great promise for mapping a diverse range of computational models for in-memory computation, with recent ReRAM-CAM designs proposed but few experimentally demonstrated. Here, programming and control of memristors across an 86 × 12 memristor ternary CAM (TCAM) array integrated with CMOS are demonstrated, and parameter tradeoffs for optimizing speed and search margin are evaluated. In addition to smaller area, this memristor TCAM results in significantly lower power due to very low programmable conductance states, motivating CAM use in a wider range of computational applications than conventional TCAMs are confined to today. Finally, the first experimental demonstration of two computational models in memristor TCAM arrays is reported: regular expression matching in a finite state machine for network security intrusion detection and definable inexact pattern matching in a Levenshtein automata for genomic sequencing.The dramatic rise of data-intensive workloads has revived application-specific computational hardware for continuing speed and power improvements, frequently achieved by limiting data movement and implementing "in-memory computation". However, conventional complementary metal oxide semiconductor (CMOS) circuit designs can still suffer low power efficiency, motivating designs leveraging nonvolatile resistive random access memory (ReRAM), and with many studies focusing on crossbar circuit architectures. Another circuit primitive-content addressable memory (CAM)-shows great promise for mapping a diverse range of computational models for in-memory computation, with recent ReRAM-CAM designs proposed but few experimentally demonstrated. Here, programming and control of memristors across an 86 × 12 memristor ternary CAM (TCAM) array integrated with CMOS are demonstrated, and parameter tradeoffs for optimizing speed and search margin are evaluated. In addition to smaller area, this memristor TCAM results in significantly lower power due to very low programmable conductance states, motivating CAM use in a wider range of computational applications than conventional TCAMs are confined to today. Finally, the first experimental demonstration of two computational models in memristor TCAM arrays is reported: regular expression matching in a finite state machine for network security intrusion detection and definable inexact pattern matching in a Levenshtein automata for genomic sequencing.
Author	Sheng, Xia Graves, Catherine E. Strachan, John Paul Miller, Darrin Kiyama, Lennie Ignowski, Jim Li, Can
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Snippet	The dramatic rise of data‐intensive workloads has revived application‐specific computational hardware for continuing speed and power improvements, frequently... The dramatic rise of data-intensive workloads has revived application-specific computational hardware for continuing speed and power improvements, frequently...
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SubjectTerms	Arrays Associative memory Automata theory Circuit design CMOS Computation content addressable memory Finite state machines in‐memory computing Mapping Materials science Memristors Pattern matching Power efficiency Power management Random access memory Resistance
Title	In‐Memory Computing with Memristor Content Addressable Memories for Pattern Matching
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