Latency, occupancy, and bandwidth in DSM multiprocessors: a performance evaluation

While the desire to use commodity parts in the communication architecture of a DSM multiprocessor offers advantages in cost and design time, the impact on application performance is unclear. We study this performance impact through detailed simulation, analytical modeling, and experiments on a flexi...

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Bibliographic Details

Published in:	IEEE transactions on computers Vol. 52; no. 7; pp. 862 - 880
Main Authors:	Chaudhuri, M., Heinrich, M., Holt, C., Singh, J.P., Rothberg, E., Hennessy, J.
Format:	Journal Article
Language:	English
Published:	New York IEEE 01.07.2003 The Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subjects:	Architecture Bandwidth Computer simulation Distributed memory Mathematical models Multiprocessor Network switching Networks Parallel architectures Prototypes Studies Virtual computers
ISSN:	0018-9340, 1557-9956
Online Access:	Get full text
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