Automatic test case generation from Simulink/Stateflow models using model checking

SUMMARYModel‐based test generation techniques based on random input generation and guided simulation do not satisfy the demands of high test coverage and completeness guarantees as required by safety‐critical applications. Recently, test generation techniques based on model checking have been report...

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Vydáno v:Software testing, verification & reliability Ročník 24; číslo 2; s. 155 - 180
Hlavní autoři: Mohalik, Swarup, Gadkari, Ambar A., Yeolekar, Anand, Shashidhar, K.C., Ramesh, S.
Médium: Journal Article
Jazyk:angličtina
Vydáno: Chichester Blackwell Publishing Ltd 01.03.2014
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ISSN:0960-0833, 1099-1689
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Shrnutí:SUMMARYModel‐based test generation techniques based on random input generation and guided simulation do not satisfy the demands of high test coverage and completeness guarantees as required by safety‐critical applications. Recently, test generation techniques based on model checking have been reported to bridge this gap. To evaluate the effectiveness of these techniques, an in‐house tool suite, AutoMOTGen, has been developed for Simulink/Stateflow and applied on real‐life case studies at General Motors. This paper outlines the test generation methodology of AutoMOTGen and gives a comparative study with a commercial, primarily random input‐based, test generation tool on the same set of examples. The results indicate that in terms of coverage, model checking‐based techniques complement the random input‐based techniques. In addition, they provide proofs for unreachability that can aid in debugging the models. Therefore, it is recommended that model checking‐based tools be utilized to complement and enhance the effectiveness of model‐based testing methods in safety‐critical systems engineering. Copyright © 2013 John Wiley & Sons, Ltd. In this paper, model checking‐based techniques are shown to complement the existing random inputbased and simulation‐based methods in model‐based testing of safety‐critical embedded systems. They are also shown to enhance the effectiveness of test coverage by providing proofs of unreachability that also aids in debugging. Copyright © 2013 John Wiley & Sons, Ltd.
Bibliografie:ArticleID:STVR1489
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ISSN:0960-0833
1099-1689
DOI:10.1002/stvr.1489