Performance evaluation of the Cray X1 distributed shared-memory architecture

The Cray X1 supercomputer, introduced in 2002, has several interesting architectural features. Two key features are the X1's distributed shared memory and its vector multiprocessors. The Cray X1 supercomputer's distributed shared memory presents a 64-bit global address space that is direct...

Celý popis

Uložené v:
Podrobná bibliografia
Vydané v:IEEE MICRO Ročník 25; číslo 1; s. 30 - 40
Hlavní autori: Dunigan, T.H., Vetter, J.S., White, J.B., Worley, P.H.
Médium: Journal Article
Jazyk:English
Vydavateľské údaje: IEEE 01.01.2005
Predmet:
Application software
Bandwidth
CMOS technology
Hardware
Memory architecture
Multiprocessor interconnection networks
Parallel processing
Parallel programming
Supercomputers
System software
ISSN:0272-1732
On-line prístup:Získať plný text
Tagy: Pridať tag
Žiadne tagy, Buďte prvý, kto otaguje tento záznam!
Popis
Shrnutí:The Cray X1 supercomputer, introduced in 2002, has several interesting architectural features. Two key features are the X1's distributed shared memory and its vector multiprocessors. The Cray X1 supercomputer's distributed shared memory presents a 64-bit global address space that is directly addressable from every MSP with an interconnect bandwidth per computation rate of 1 byte/flop. In this article, we characterize the performance of the X1's distributed shared-memory system and its interconnection network using microbench-marks and applications.
Bibliografia:ObjectType-Article-2
SourceType-Scholarly Journals-1
ObjectType-Feature-1
content type line 23
ISSN:0272-1732
DOI:10.1109/MM.2005.20