An optimizing technique for using MATLAB HDL coder
Background MathWorks has provided an invaluable tool for designing and implementing FPGAs. MATLAB HDL coder serves a dual purpose, providing a quick proof of concept on the one hand and providing the g an easy-to-use platform for testing and verification on the other. It has main drawbacks over thes...
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| Vydáno v: | Bulletin of the National Research Centre Ročník 47; číslo 1; s. 94 - 8 |
|---|---|
| Hlavní autoři: | , |
| Médium: | Journal Article |
| Jazyk: | angličtina |
| Vydáno: |
Berlin/Heidelberg
Springer Berlin Heidelberg
01.12.2023
Springer Nature B.V SpringerOpen |
| Témata: | |
| ISSN: | 2522-8307, 2522-8307 |
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| Abstract | Background
MathWorks has provided an invaluable tool for designing and implementing FPGAs. MATLAB HDL coder serves a dual purpose, providing a quick proof of concept on the one hand and providing the g an easy-to-use platform for testing and verification on the other. It has main drawbacks over these advantages; it generates a code that is not optimized for both area and frequency.
Results
In this paper, we provide a technique for optimizing both area and frequency without losing the main advantages. The most affecting problem we found is loops. This paper classifies loop writing purposes into two types. The first one is preferable and introduces ease of writing a few lines instead of repeating the code. The second type is the problem that we intended to solve. Type II loop is appearing when the algorithm should perform these lines for several clock cycles. Writing it traditionally, force the synthesizer to implement all the repetitive clock cycles as repetitive hardware to be done in one clock cycle. This clock cycle is wide in time and is slow in frequency. This paper introduces an optimization technique for this problem. We compare before and after the implementation of our proposed technique.
Conclusions
We used Xilinx Spartan 6 XC6SLX4-2CPG196 FPGA. Our proposed technique improves the number of slice LUTs (Look Up Tables) requirement from 366 to 72%. The frequency improved from: 26.574 to 185.355 MHz. Based on that, we now recommend using MATLAB HDL coder in FPGA Design. |
|---|---|
| AbstractList | BackgroundMathWorks has provided an invaluable tool for designing and implementing FPGAs. MATLAB HDL coder serves a dual purpose, providing a quick proof of concept on the one hand and providing the g an easy-to-use platform for testing and verification on the other. It has main drawbacks over these advantages; it generates a code that is not optimized for both area and frequency.ResultsIn this paper, we provide a technique for optimizing both area and frequency without losing the main advantages. The most affecting problem we found is loops. This paper classifies loop writing purposes into two types. The first one is preferable and introduces ease of writing a few lines instead of repeating the code. The second type is the problem that we intended to solve. Type II loop is appearing when the algorithm should perform these lines for several clock cycles. Writing it traditionally, force the synthesizer to implement all the repetitive clock cycles as repetitive hardware to be done in one clock cycle. This clock cycle is wide in time and is slow in frequency. This paper introduces an optimization technique for this problem. We compare before and after the implementation of our proposed technique.ConclusionsWe used Xilinx Spartan 6 XC6SLX4-2CPG196 FPGA. Our proposed technique improves the number of slice LUTs (Look Up Tables) requirement from 366 to 72%. The frequency improved from: 26.574 to 185.355 MHz. Based on that, we now recommend using MATLAB HDL coder in FPGA Design. Abstract Background MathWorks has provided an invaluable tool for designing and implementing FPGAs. MATLAB HDL coder serves a dual purpose, providing a quick proof of concept on the one hand and providing the g an easy-to-use platform for testing and verification on the other. It has main drawbacks over these advantages; it generates a code that is not optimized for both area and frequency. Results In this paper, we provide a technique for optimizing both area and frequency without losing the main advantages. The most affecting problem we found is loops. This paper classifies loop writing purposes into two types. The first one is preferable and introduces ease of writing a few lines instead of repeating the code. The second type is the problem that we intended to solve. Type II loop is appearing when the algorithm should perform these lines for several clock cycles. Writing it traditionally, force the synthesizer to implement all the repetitive clock cycles as repetitive hardware to be done in one clock cycle. This clock cycle is wide in time and is slow in frequency. This paper introduces an optimization technique for this problem. We compare before and after the implementation of our proposed technique. Conclusions We used Xilinx Spartan 6 XC6SLX4-2CPG196 FPGA. Our proposed technique improves the number of slice LUTs (Look Up Tables) requirement from 366 to 72%. The frequency improved from: 26.574 to 185.355 MHz. Based on that, we now recommend using MATLAB HDL coder in FPGA Design. Background MathWorks has provided an invaluable tool for designing and implementing FPGAs. MATLAB HDL coder serves a dual purpose, providing a quick proof of concept on the one hand and providing the g an easy-to-use platform for testing and verification on the other. It has main drawbacks over these advantages; it generates a code that is not optimized for both area and frequency. Results In this paper, we provide a technique for optimizing both area and frequency without losing the main advantages. The most affecting problem we found is loops. This paper classifies loop writing purposes into two types. The first one is preferable and introduces ease of writing a few lines instead of repeating the code. The second type is the problem that we intended to solve. Type II loop is appearing when the algorithm should perform these lines for several clock cycles. Writing it traditionally, force the synthesizer to implement all the repetitive clock cycles as repetitive hardware to be done in one clock cycle. This clock cycle is wide in time and is slow in frequency. This paper introduces an optimization technique for this problem. We compare before and after the implementation of our proposed technique. Conclusions We used Xilinx Spartan 6 XC6SLX4-2CPG196 FPGA. Our proposed technique improves the number of slice LUTs (Look Up Tables) requirement from 366 to 72%. The frequency improved from: 26.574 to 185.355 MHz. Based on that, we now recommend using MATLAB HDL coder in FPGA Design. |
| ArticleNumber | 94 |
| Author | Kayed, Somaya Elsayed, Ghada |
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| References | Digilent: Cmod S6 FPGA Board Reference Manual (2023) https://digilent.com/reference/_media/reference/programmable-logic/cmod-s6/cmods6_rm.pdf Accessed 20 Feb 2023 MATHWORKS Copyright 2011-2015 The MathWorks, Inc: Advanced Encryption System (AES) (2023) https://www.mathworks.com/matlabcentral/mlc-downloads/downloads/submissions/50098/versions/3/previews/mlhdlc_tutorial_comms_aes.m/index.html Accessed 20 Feb 2023 Khudair NA, Shujaa MI, Zghair EM (2023) Iot based image processing filters. In: AIP Conference Proceedings, vol 2591, AIP Publishing LLC, p 020007 Neelima K, Meruva KR, Subhas C (2023) Image fusion using xilinx system generator for mri and ct medical image modalities. In: 2023 International Conference on Emerging Smart Computing and Informatics (ESCI), pp 1– 5 ElsayedGKayedSA comparative study between matlab hdl coder and vhdl for FPGAs design and implementationJ Int Soc Sci Eng202244929810.21608/jisse.2022.136645.1056 Loganathan P, Karthikeyan R (2023) Combination of wavelet transform and sobel operator using xilinx system generator for edge detection in medical plant leaf. In: Computational Vision and Bio-Inspired Computing: Proceedings of ICCVBIC 2022, Springer, pp 333– 341 SemmadABahouraMScalable serial hardware architecture of multilayer perceptron neural network for automatic wheezing detectionMicroprocess Microsyst20239910.1016/j.micpro.2023.104844 SankarDLakshmiSBabuCMathewKRapid prototyping of predictive direct current control in a low-cost fpga using hdl coderInt J Power Energy Syst202343101910.2316/J.2023.203-0437 Bendahane B, Jenkal W, Laaboubi M, Latif R (2023) Hdl coder tool for ecg signal denoising. In: Digital Technologies and Applications: Proceedings of ICDTA’23, Fez, Morocco, Vol 1, pp 753– 760. Springer Wallace NL (2023) Developing firmware for space weather probes 2 using HDL coder. Thesis on Master of Science (MS), Electrical and Computer Engineering Commons, Utah State University, Date of Award 8-2023. https://doi.org/10.26076/b311-3847 ZamiriESanchezAYushkovaMMartínez-GarcíaMSde CastroAComparison of different design alternatives for hardware-in-the-loop of power convertersElectronics202110892610.3390/electronics10080926 Mathworks: Initialize Persistent Variables in MATLAB Functions (2022) https://www.mathworks.com/help/simulink/ug/initialize-persistent-variables.html Accessed 20 Feb 2023 MATHWORKS: Speed and Area Optimization (2022) Improvements through resource sharing, streaming, pipelining, RAM mapping. https://www.mathworks.com/help/hdlcoder/speed-and-area-optimization-1.html Accessed 20 Feb 2023 MathWorks, inc: HDL CoderTM\documentclass[12pt]{minimal} \usepackage{amsmath} \usepackage{wasysym} \usepackage{amsfonts} \usepackage{amssymb} \usepackage{amsbsy} \usepackage{mathrsfs} \usepackage{upgreek} \setlength{\oddsidemargin}{-69pt} \begin{document}$$^{\rm TM}$$\end{document} User’s GuideCOPYRIGHT 2012-2015 (2012) https://www.mathworks.com/help/hdlcoder/ Accessed 20 Feb 2023 NandakrishnanRArjunSNandakumarCNSajeshSHarikrishananKDeviPAAdaptive beamforming using minimum variance distortionless responseInt J Res Eng Sci Manag2023642730 Rajaby E, Sayedi SM, Yazdian E (2023) Hardware design and implementation of high-efficiency cube-root of complex numbers. Microprocess Microsyst. https://doi.org/10.1016/j.micpro.2023.104847 FIPS 197: Advanced Encryption Standard (AES) (2001). https://csrc.nist.gov/publications/detail/fips/197/final Accessed 20 Feb 2023 Lopez-RamirezMLedesma-CarrilloLMRodriguez-DonateCMiranda-VidalesHMata-ChavezRICabal-YepezEFpga-based online voltage/current swell segmentation and measurementComput Electr Eng202310710.1016/j.compeleceng.2023.108620 KmADuttaguptaSHdl-ready mac layer implementation for multi-node Li-Fi communicationsInt J Inf Technol202310.1007/s41870-023-01255-1 Havinga T, Jiao X, Liu W, Moerman I (2023) Accelerating fpga-based wi-fi transceiver design and prototyping by high-level synthesis. arXiv preprint arXiv:2305.13351 ZafarAPerformance of FPGA-based implementations of data classification techniques using HDL coder2022Long BeachCalifornia State University HamdaouiFSaklyAAutomatic diagnostic system for segmentation of 3d/2d brain mri images based on a hardware architectureMicroprocess Microsyst20239810.1016/j.micpro.2023.104814 David Hill: Advanced Encryption Standard (AES)-128,192, 256 (2021) https://www.mathworks.com/matlabcentral/fileexchange/73412-advanced-encryption-standard-aes-128-192-256 Accessed 20 Feb 2023 Naiem GF, Elramly S, Hasan BE, Shehata K (2008) An efficient implementation of cbc mode rijndeal aes on an fpga. In: 2008 National Radio Science Conference, pp 1– 8 Dasgupta S (1989) Computer architecture: a modern synthesis. Vol 1, John Wiley & Sons 1066_CR9 1066_CR8 1066_CR7 1066_CR5 1066_CR4 1066_CR10 1066_CR1 1066_CR11 D Sankar (1066_CR3) 2023; 43 1066_CR18 A Semmad (1066_CR12) 2023; 99 1066_CR19 A Km (1066_CR2) 2023 F Hamdaoui (1066_CR13) 2023; 98 G Elsayed (1066_CR16) 2022; 4 1066_CR21 1066_CR22 A Zafar (1066_CR15) 2022 1066_CR20 1066_CR25 1066_CR23 1066_CR24 M Lopez-Ramirez (1066_CR14) 2023; 107 E Zamiri (1066_CR17) 2021; 10 R Nandakrishnan (1066_CR6) 2023; 6 |
| References_xml | – reference: ZamiriESanchezAYushkovaMMartínez-GarcíaMSde CastroAComparison of different design alternatives for hardware-in-the-loop of power convertersElectronics202110892610.3390/electronics10080926 – reference: MathWorks, inc: HDL CoderTM\documentclass[12pt]{minimal} \usepackage{amsmath} \usepackage{wasysym} \usepackage{amsfonts} \usepackage{amssymb} \usepackage{amsbsy} \usepackage{mathrsfs} \usepackage{upgreek} \setlength{\oddsidemargin}{-69pt} \begin{document}$$^{\rm TM}$$\end{document} User’s GuideCOPYRIGHT 2012-2015 (2012) https://www.mathworks.com/help/hdlcoder/ Accessed 20 Feb 2023 – reference: ElsayedGKayedSA comparative study between matlab hdl coder and vhdl for FPGAs design and implementationJ Int Soc Sci Eng202244929810.21608/jisse.2022.136645.1056 – reference: Khudair NA, Shujaa MI, Zghair EM (2023) Iot based image processing filters. In: AIP Conference Proceedings, vol 2591, AIP Publishing LLC, p 020007 – reference: FIPS 197: Advanced Encryption Standard (AES) (2001). https://csrc.nist.gov/publications/detail/fips/197/final Accessed 20 Feb 2023 – reference: Lopez-RamirezMLedesma-CarrilloLMRodriguez-DonateCMiranda-VidalesHMata-ChavezRICabal-YepezEFpga-based online voltage/current swell segmentation and measurementComput Electr Eng202310710.1016/j.compeleceng.2023.108620 – reference: MATHWORKS: Speed and Area Optimization (2022) Improvements through resource sharing, streaming, pipelining, RAM mapping. https://www.mathworks.com/help/hdlcoder/speed-and-area-optimization-1.html Accessed 20 Feb 2023 – reference: Rajaby E, Sayedi SM, Yazdian E (2023) Hardware design and implementation of high-efficiency cube-root of complex numbers. Microprocess Microsyst. https://doi.org/10.1016/j.micpro.2023.104847 – reference: SankarDLakshmiSBabuCMathewKRapid prototyping of predictive direct current control in a low-cost fpga using hdl coderInt J Power Energy Syst202343101910.2316/J.2023.203-0437 – reference: KmADuttaguptaSHdl-ready mac layer implementation for multi-node Li-Fi communicationsInt J Inf Technol202310.1007/s41870-023-01255-1 – reference: MATHWORKS Copyright 2011-2015 The MathWorks, Inc: Advanced Encryption System (AES) (2023) https://www.mathworks.com/matlabcentral/mlc-downloads/downloads/submissions/50098/versions/3/previews/mlhdlc_tutorial_comms_aes.m/index.html Accessed 20 Feb 2023 – reference: David Hill: Advanced Encryption Standard (AES)-128,192, 256 (2021) https://www.mathworks.com/matlabcentral/fileexchange/73412-advanced-encryption-standard-aes-128-192-256 Accessed 20 Feb 2023 – reference: Mathworks: Initialize Persistent Variables in MATLAB Functions (2022) https://www.mathworks.com/help/simulink/ug/initialize-persistent-variables.html Accessed 20 Feb 2023 – reference: Naiem GF, Elramly S, Hasan BE, Shehata K (2008) An efficient implementation of cbc mode rijndeal aes on an fpga. In: 2008 National Radio Science Conference, pp 1– 8 – reference: Loganathan P, Karthikeyan R (2023) Combination of wavelet transform and sobel operator using xilinx system generator for edge detection in medical plant leaf. In: Computational Vision and Bio-Inspired Computing: Proceedings of ICCVBIC 2022, Springer, pp 333– 341 – reference: Wallace NL (2023) Developing firmware for space weather probes 2 using HDL coder. Thesis on Master of Science (MS), Electrical and Computer Engineering Commons, Utah State University, Date of Award 8-2023. https://doi.org/10.26076/b311-3847 – reference: NandakrishnanRArjunSNandakumarCNSajeshSHarikrishananKDeviPAAdaptive beamforming using minimum variance distortionless responseInt J Res Eng Sci Manag2023642730 – reference: Digilent: Cmod S6 FPGA Board Reference Manual (2023) https://digilent.com/reference/_media/reference/programmable-logic/cmod-s6/cmods6_rm.pdf Accessed 20 Feb 2023 – reference: Bendahane B, Jenkal W, Laaboubi M, Latif R (2023) Hdl coder tool for ecg signal denoising. In: Digital Technologies and Applications: Proceedings of ICDTA’23, Fez, Morocco, Vol 1, pp 753– 760. Springer – reference: HamdaouiFSaklyAAutomatic diagnostic system for segmentation of 3d/2d brain mri images based on a hardware architectureMicroprocess Microsyst20239810.1016/j.micpro.2023.104814 – reference: ZafarAPerformance of FPGA-based implementations of data classification techniques using HDL coder2022Long BeachCalifornia State University – reference: Havinga T, Jiao X, Liu W, Moerman I (2023) Accelerating fpga-based wi-fi transceiver design and prototyping by high-level synthesis. arXiv preprint arXiv:2305.13351 – reference: Dasgupta S (1989) Computer architecture: a modern synthesis. Vol 1, John Wiley & Sons – reference: Neelima K, Meruva KR, Subhas C (2023) Image fusion using xilinx system generator for mri and ct medical image modalities. In: 2023 International Conference on Emerging Smart Computing and Informatics (ESCI), pp 1– 5 – reference: SemmadABahouraMScalable serial hardware architecture of multilayer perceptron neural network for automatic wheezing detectionMicroprocess Microsyst20239910.1016/j.micpro.2023.104844 – ident: 1066_CR7 doi: 10.1109/FCCM57271.2023.00047 – volume: 99 year: 2023 ident: 1066_CR12 publication-title: Microprocess Microsyst doi: 10.1016/j.micpro.2023.104844 – ident: 1066_CR1 – volume-title: Performance of FPGA-based implementations of data classification techniques using HDL coder year: 2022 ident: 1066_CR15 – volume: 10 start-page: 926 issue: 8 year: 2021 ident: 1066_CR17 publication-title: Electronics doi: 10.3390/electronics10080926 – ident: 1066_CR5 doi: 10.26076/b311-3847 – volume: 4 start-page: 92 issue: 4 year: 2022 ident: 1066_CR16 publication-title: J Int Soc Sci Eng doi: 10.21608/jisse.2022.136645.1056 – ident: 1066_CR21 – ident: 1066_CR23 – ident: 1066_CR25 doi: 10.1109/NRSC.2008.4542373 – ident: 1066_CR8 doi: 10.1016/j.micpro.2023.104847 – ident: 1066_CR4 doi: 10.1007/978-3-031-29857-8_75 – ident: 1066_CR10 – ident: 1066_CR11 doi: 10.1063/5.0135017 – ident: 1066_CR18 – volume: 98 year: 2023 ident: 1066_CR13 publication-title: Microprocess Microsyst doi: 10.1016/j.micpro.2023.104814 – ident: 1066_CR20 – ident: 1066_CR22 – ident: 1066_CR24 – volume: 43 start-page: 1 issue: 10 year: 2023 ident: 1066_CR3 publication-title: Int J Power Energy Syst doi: 10.2316/J.2023.203-0437 – volume: 107 year: 2023 ident: 1066_CR14 publication-title: Comput Electr Eng doi: 10.1016/j.compeleceng.2023.108620 – ident: 1066_CR9 doi: 10.1007/978-981-19-9819-5_25 – volume: 6 start-page: 27 issue: 4 year: 2023 ident: 1066_CR6 publication-title: Int J Res Eng Sci Manag – year: 2023 ident: 1066_CR2 publication-title: Int J Inf Technol doi: 10.1007/s41870-023-01255-1 – ident: 1066_CR19 |
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MathWorks has provided an invaluable tool for designing and implementing FPGAs. MATLAB HDL coder serves a dual purpose, providing a quick proof of... BackgroundMathWorks has provided an invaluable tool for designing and implementing FPGAs. MATLAB HDL coder serves a dual purpose, providing a quick proof of... Abstract Background MathWorks has provided an invaluable tool for designing and implementing FPGAs. MATLAB HDL coder serves a dual purpose, providing a quick... |
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| SubjectTerms | AES Agriculture Algorithms Engineering Field programmable gate arrays FPGA High density lipoprotein Humanities and Social Sciences Lookup tables Matlab MATLAB HDL coder multidisciplinary Optimization Optimization techniques Science Science (multidisciplinary) |
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| Title | An optimizing technique for using MATLAB HDL coder |
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