Fast implementation of dense stereo vision algorithms on a highly parallel SIMD architecture

In this paper, we present faster than real-time implementation of a class of dense stereo vision algorithms on a low-power massively parallel SIMD architecture, the CSX700. With two cores, each with 96 Processing Elements, this SIMD architecture provides a peak computation power of 96 GFLOPS while c...

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Vydáno v:Journal of real-time image processing Ročník 8; číslo 4; s. 421 - 435
Hlavní autoři: Hosseini, Fouzhan, Fijany, Amir, Safari, Saeed, Fontaine, Jean-Guy
Médium: Journal Article
Jazyk:angličtina
Vydáno: Berlin/Heidelberg Springer Berlin Heidelberg 01.12.2013
Springer
Springer Nature B.V
Témata:
Algorithms
Applied sciences
Artificial intelligence
Computer Graphics
Computer Science
Computer science; control theory; systems
Computer systems and distributed systems. User interface
Computer vision
Electronics
Exact sciences and technology
Flexibility
Frames per second
Image Processing and Computer Vision
Integrated circuits
Integrated circuits by function (including memories and processors)
Multimedia Information Systems
Original Research Paper
Pattern Recognition
Pattern recognition. Digital image processing. Computational geometry
Real time
Semiconductor electronics. Microelectronics. Optoelectronics. Solid state devices
Signal,Image and Speech Processing
Software
Storage and reproduction of information
Parallel computation
Dense stereo vision algorithms
SIMD parallel architecture
High performance
Computer vision
Parallel algorithm
Correlation
Stereo image processing
High definition television
SIMD computer
Low power
Real time
Distributed computing
Boarded computer
Vector processor
Solid state device
Massive parallelism
Disparity
Stereopsis
Peak power
Semiconductor storage
Parallelization
ISSN:1861-8200, 1861-8219
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Shrnutí:In this paper, we present faster than real-time implementation of a class of dense stereo vision algorithms on a low-power massively parallel SIMD architecture, the CSX700. With two cores, each with 96 Processing Elements, this SIMD architecture provides a peak computation power of 96 GFLOPS while consuming only 9 Watts, making it an excellent candidate for embedded computing applications. Exploiting full features of this architecture, we have developed schemes for an efficient parallel implementation with minimum of overhead. For the sum of squared differences (SSD) algorithm and for VGA (640 × 480) images with disparity ranges of 16 and 32, we achieve a performance of 179 and 94 frames per second (fps), respectively. For the HDTV (1,280 × 720) images with disparity ranges of 16 and 32, we achieve a performance of 67 and 35 fps, respectively. We have also implemented more accurate, and hence more computationally expensive variants of the SSD, and for most cases, particularly for VGA images, we have achieved faster than real-time performance. Our results clearly demonstrate that, by developing careful parallelization schemes, the CSX architecture can provide excellent performance and flexibility for various embedded vision applications.
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ISSN:1861-8200
1861-8219
DOI:10.1007/s11554-011-0211-z