VLSI implementation of low‐power cost‐efficient lossless ECG encoder design for wireless healthcare monitoring application

An efficient VLSI architecture of a lossless ECG encoding circuit is proposed for wireless healthcare monitoring applications. To reduce the transmission and storage data, a novel lossless compression algorithm is proposed for ECG signal compression. It consists of a novel adaptive rending predictor...

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Vydané v:Electronics letters Ročník 49; číslo 2; s. 91 - 93
Hlavní autori: Chen, S.‐L., Wang, J.‐G
Médium: Journal Article
Jazyk:English
Vydavateľské údaje: Stevenage The Institution of Engineering and Technology 01.01.2013
Institution of Engineering and Technology
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ISSN:1350-911X, 0013-5194, 1350-911X
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Abstract An efficient VLSI architecture of a lossless ECG encoding circuit is proposed for wireless healthcare monitoring applications. To reduce the transmission and storage data, a novel lossless compression algorithm is proposed for ECG signal compression. It consists of a novel adaptive rending predictor and a novel two‐stage entropy encoder based on two Huffman coding tables. The proposed lossless ECG encoder design was implemented using only simple arithmetic units. To improve the performance, the proposed ECG encoder was designed by pipeline technology and implemented the two‐stage entropy encoder by the architecture of a look‐up table. The VLSI architecture of this work contains 3.55 K gate counts and its core area is 45987 µm2 synthesised by a 0.18 µm CMOS process. It can operate at 100 MHz processing rate with only 36.4 µW. The data compression rate reaches an average value 2.43 for the MIT‐BIH Arrhythmia Database. Compared with the previous low‐complexity and high performance techniques, this work achieves lower hardware cost, lower power consumption, and a better compression rate than other lossless ECG encoder designs.
AbstractList An efficient VLSI architecture of a lossless ECG encoding circuit is proposed for wireless healthcare monitoring applications. To reduce the transmission and storage data, a novel lossless compression algorithm is proposed for ECG signal compression. It consists of a novel adaptive rending predictor and a novel two‐stage entropy encoder based on two Huffman coding tables. The proposed lossless ECG encoder design was implemented using only simple arithmetic units. To improve the performance, the proposed ECG encoder was designed by pipeline technology and implemented the two‐stage entropy encoder by the architecture of a look‐up table. The VLSI architecture of this work contains 3.55 K gate counts and its core area is 45987 µm 2 synthesised by a 0.18 µm CMOS process. It can operate at 100 MHz processing rate with only 36.4 µW. The data compression rate reaches an average value 2.43 for the MIT‐BIH Arrhythmia Database. Compared with the previous low‐complexity and high performance techniques, this work achieves lower hardware cost, lower power consumption, and a better compression rate than other lossless ECG encoder designs.
An efficient VLSI architecture of a lossless ECG encoding circuit is proposed for wireless healthcare monitoring applications. To reduce the transmission and storage data, a novel lossless compression algorithm is proposed for ECG signal compression. It consists of a novel adaptive rending predictor and a novel two‐stage entropy encoder based on two Huffman coding tables. The proposed lossless ECG encoder design was implemented using only simple arithmetic units. To improve the performance, the proposed ECG encoder was designed by pipeline technology and implemented the two‐stage entropy encoder by the architecture of a look‐up table. The VLSI architecture of this work contains 3.55 K gate counts and its core area is 45987 µm2 synthesised by a 0.18 µm CMOS process. It can operate at 100 MHz processing rate with only 36.4 µW. The data compression rate reaches an average value 2.43 for the MIT‐BIH Arrhythmia Database. Compared with the previous low‐complexity and high performance techniques, this work achieves lower hardware cost, lower power consumption, and a better compression rate than other lossless ECG encoder designs.
Author Wang, J.‐G
Chen, S.‐L.
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10.1049/el:20081319
10.1049/el.2010.3191
10.1109/TCE.2011.5735512
10.1109/TBME.2006.888820
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Issue 2
Keywords Signal compression
High performance
Lossless circuit
VLSI circuit
Circuit design
Pipeline processor
Huffman code
Data compression
Lossless compression
Information rate
Low power
Adaptive method
Energy savings
Pipeline
Storage
Electrocardiography
Wireless network
Arrhythmia (physiology)
Monitoring
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References 2009; 3
2007; 54
2011; 57
2008; 44
2011; 47
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SubjectTerms adaptive rending predictor
Applied sciences
arithmetic unit
Biological and medical sciences
CMOS integrated circuits
CMOS process
Coding, codes
computerised monitoring
data compression
ECG signal compression
electrocardiography
Electrocardiography. Vectocardiography
Electrodiagnosis. Electric activity recording
Electronics
entropy codes
entropy encoder
Exact sciences and technology
frequency
frequency 100 MHz
gate counts
health care
Huffman codes
Huffman coding table
Information, signal and communications theory
Integrated circuits
Integrated circuits by function (including memories and processors)
Investigative techniques, diagnostic techniques (general aspects)
lookup table
lossless compression algorithm
lossless ECG encoder design
Medical sciences
medical signal processing
MIT‐BIH Arrhythmia database
Pathology. Cytology. Biochemistry. Spectrometry. Miscellaneous investigative techniques
patient monitoring
pipeline arithmetic
pipeline technology
power
power 36.4 muW
Semiconductor electronics. Microelectronics. Optoelectronics. Solid state devices
Signal and communications theory
size
size 0.18 mum
table lookup
Telecommunications and information theory
VLSI
VLSI architecture
wireless healthcare monitoring application
Title VLSI implementation of low‐power cost‐efficient lossless ECG encoder design for wireless healthcare monitoring application
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