Low-complexity bit-parallel systolic Montgomery multipliers for special classes of GF(2/sup m/)

Recently, cryptographic applications based on finite fields have attracted much interest. This paper presents a transformation method to implement low-complexity Montgomery multipliers for all-one polynomials and trinomials. Using this method, we propose a new bit-parallel systolic architecture for...

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Vydáno v:IEEE transactions on computers Ročník 54; číslo 9; s. 1061 - 1070
Hlavní autoři: Lee, Chiou-Yng, Horng, Jenn-Shyong, Jou, I-Chang, Lu, Erl-Huei
Médium: Journal Article
Jazyk:angličtina
Vydáno: New York IEEE 01.09.2005
The Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Témata:
Circuits
Clocks
Cryptography
Digital arithmetic
finite field
Galois fields
Gates (circuits)
Index Terms- Bit-parallel systolic multiplier
Interconnection
irreducible AOP
irreducible trinomial
Mathematical analysis
montgomery multiplication
Multipliers
Multiplying circuits
Parallel architectures
Polynomials
Transformations
ISSN:0018-9340, 1557-9956
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Shrnutí:Recently, cryptographic applications based on finite fields have attracted much interest. This paper presents a transformation method to implement low-complexity Montgomery multipliers for all-one polynomials and trinomials. Using this method, we propose a new bit-parallel systolic architecture for computing multiplications over GF(2/sup m/). These new multipliers have a latency m+1 clock cycles and each cell incorporates at most one 2-input AND gate, two 2-input XOR gates, and four 1-bit latches. Moreover, these new multipliers are shown to exhibit significantly lower latency and circuit complexity than the related systolic multipliers and are highly appropriate for VLSI systems because of their regular interconnection pattern, modular structure, and fully inherent parallelism.
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ISSN:0018-9340
1557-9956
DOI:10.1109/TC.2005.147