An efficient algorithmic framework to minimize the summand matrix in binary multiplication

Binary multiplication is a key operation in digital systems, often limited by the complexity of generating and summing numerous partial products. Traditional methods, like Booth’s algorithm, produce a summand matrix proportional to the operand bit-length, increasing computational load, hardware usag...

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Vydáno v:Automatika Ročník 66; číslo 4; s. 22 - 31
Hlavní autoři: Verma, Amit, Prateek, Manish, Shivhare, Shiv Naresh, Singh, Thipendra P., Kumar, Anuj, Ranjan, Rakesh, Priyadarshi, Rahul
Médium: Journal Article
Jazyk:angličtina
Vydáno: Ljubljana Taylor & Francis Ltd 02.10.2025
Taylor & Francis Group
Témata:
Algorithms
Arithmetic and logic units
Binary multiplication
Booth’s algorithm
Complexity
Digital systems
Embedded systems
Hardware
hardware efficiency
latency optimization
Multiplication
multiplier
summand reduction
ISSN:0005-1144, 1848-3380
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Shrnutí:Binary multiplication is a key operation in digital systems, often limited by the complexity of generating and summing numerous partial products. Traditional methods, like Booth’s algorithm, produce a summand matrix proportional to the operand bit-length, increasing computational load, hardware usage and latency. To address these issues, we propose a novel binary multiplication algorithm that minimizes the number of required summands. By selectively using the smaller operand and employing targeted shift operations, our method avoids recursive bit-level multiplications and reduces summands to as few as 1–5 for odd and 1–4 for even operands. This approach achieves a lower time complexity of O(log2n), offering significant speed improvements over existing algorithms. Moreover, it leads to a reduction in hardware components by approximately 40–75%, contributing to notable power savings. The algorithm is fully compatible with existing parallel adder circuits, ensuring ease of integration. Its simplicity and efficiency make it ideal for low-power arithmetic units, embedded systems and DSP applications. Future work will focus on supporting signed multiplications and integrating the algorithm into VLSI designs for real-world applications, enhancing its appeal in resource-constrained computing environments.
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ISSN:0005-1144
1848-3380
DOI:10.1080/00051144.2025.2526261