An efficient algorithmic framework to minimize the summand matrix in binary multiplication

Binary multiplication is a key operation in digital systems, often limited by the complexity of generating and summing numerous partial products. Traditional methods, like Booth’s algorithm, produce a summand matrix proportional to the operand bit-length, increasing computational load, hardware usag...

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Bibliographic Details

Published in:	Automatika Vol. 66; no. 4; pp. 22 - 31
Main Authors:	Verma, Amit, Prateek, Manish, Shivhare, Shiv Naresh, Singh, Thipendra P., Kumar, Anuj, Ranjan, Rakesh, Priyadarshi, Rahul
Format:	Journal Article
Language:	English
Published:	Ljubljana Taylor & Francis Ltd 02.10.2025 Taylor & Francis Group
Subjects:	Algorithms Arithmetic and logic units Binary multiplication Booth’s algorithm Complexity Digital systems Embedded systems Hardware hardware efficiency latency optimization Multiplication multiplier summand reduction
ISSN:	0005-1144, 1848-3380
Online Access:	Get full text
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