Design of a GF(64)-LDPC Decoder Based on the EMS Algorithm

This paper presents the architecture, performance and implementation results of a serial GF(64)-LDPC decoder based on a reduced-complexity version of the Extended Min-Sum algorithm. The main contributions of this work correspond to the variable node processing, the codeword decision and the elementa...

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Bibliographic Details
Published in:IEEE transactions on circuits and systems. I, Regular papers Vol. 60; no. 10; pp. 2644 - 2656
Main Authors: Boutillon, Emmanuel, Conde-Canencia, Laura, Al Ghouwayel, Ali
Format: Journal Article
Language:English
Published: IEEE 01.10.2013
Subjects:
Algorithm design and analysis
Complexity theory
Computer architecture
Decoding
Extended Min Sum algorithm
FPGA synthesis
Iterative decoding
low-complexity architecture
non-binary low-density parity-check decoders
Random access memory
ISSN:1549-8328, 1558-0806
Online Access:Get full text
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Summary:This paper presents the architecture, performance and implementation results of a serial GF(64)-LDPC decoder based on a reduced-complexity version of the Extended Min-Sum algorithm. The main contributions of this work correspond to the variable node processing, the codeword decision and the elementary check node processing. Post-synthesis area results show that the decoder area is less than 20% of a Virtex 4 FPGA for a decoding throughput of 2.95 Mbps. The implemented decoder presents performance at less than 0.7 dB from the Belief Propagation algorithm for different code lengths and rates. Moreover, the proposed architecture can be easily adapted to decode very high Galois Field orders, such as GF(4096) or higher, by slightly modifying a marginal part of the design.
ISSN:1549-8328
1558-0806
DOI:10.1109/TCSI.2013.2279186