Parallel custom instruction identification for extensible processors
With the ability of customization for an application domain, extensible processors have been used more and more in embedded systems in recent years. Extensible processors customize an application domain by executing parts of application code in hardware instead of software. Determining parts of appl...
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| Published in: | Journal of systems architecture Vol. 76; pp. 149 - 159 |
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| Main Authors: | , , , |
| Format: | Journal Article |
| Language: | English |
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Elsevier B.V
01.05.2017
Elsevier |
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| ISSN: | 1383-7621, 1873-6165 |
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| Abstract | With the ability of customization for an application domain, extensible processors have been used more and more in embedded systems in recent years. Extensible processors customize an application domain by executing parts of application code in hardware instead of software. Determining parts of application code as custom instruction generally requires subgraph enumeration and subgraph selection. Both subgraph enumeration problem and subgraph selection problem are computationally difficult problems. Most of previous works focus on sequential algorithms for these two problems. In this paper, we present a parallel implementation of a latest subgraph enumeration algorithm based on a computer cluster. A standard ant colony optimization algorithm (ACO), a modified version of ACO with local optimum search and a parallel ACO algorithm are also proposed to solve the subgraph selection problem in this work. Experimental results show that the parallel algorithms outperform the sequential algorithms in terms of runtime or (and) quality of results. In addition, we have formally proved the upper bound on the number of feasible solutions in subgraph selection problem with or without the overlapping constraint. |
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| AbstractList | With the ability of customization for an application domain, extensible processors have been used more and more in embedded systems in recent years. Extensible processors customize an application domain by executing parts of application code in hardware instead of software. Determining parts of application code as custom instruction generally requires subgraph enumeration and subgraph selection. Both subgraph enumeration problem and subgraph selection problem are computationally difficult problems. Most of previous works focus on sequential algorithms for these two problems. In this paper, we present a parallel implementation of a latest subgraph enumeration algorithm based on a computer cluster. A standard ant colony optimization algorithm (ACO), a modified version of ACO with local optimum search and a parallel ACO algorithm are also proposed to solve the subgraph selection problem in this work. Experimental results show that the parallel algorithms outperform the sequential algorithms in terms of runtime or (and) quality of results. In addition, we have formally proved the upper bound on the number of feasible solutions in subgraph selection problem with or without the overlapping constraint. |
| Author | Casseau, Emmanuel Xiao, Chenglong Wang, Shanshan Liu, Wanjun |
| Author_xml | – sequence: 1 givenname: Chenglong surname: Xiao fullname: Xiao, Chenglong email: chenglong.xiao@gmail.com organization: Liaoning Technical University, China – sequence: 2 givenname: Shanshan surname: Wang fullname: Wang, Shanshan email: celine.shanshan.wang@gmail.com organization: Liaoning Technical University, China – sequence: 3 givenname: Wanjun surname: Liu fullname: Liu, Wanjun email: liuwanjun39@163.com organization: Liaoning Technical University, China – sequence: 4 givenname: Emmanuel orcidid: 0000-0001-7216-749X surname: Casseau fullname: Casseau, Emmanuel email: emmanuel.casseau@irisa.fr organization: University of Rennes I, Irisa, Inria, France |
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| BookMark | eNqFkL1OwzAUhS1UJNrCGzBkZUjwtRPHZUCqSqFIlWCA2XIcW7hK48p2K_r2JA0sDDDdH51zru43QaPWtRqha8AZYGC3mywcg_QqI92UAWQY4AyNgZc0ZcCKUddTTtOSEbhAkxA2GOOiADJGD6_Sy6bRTaL2IbptYtsQ_V5F69rE1rqN1lglT6NxPtGfUbfBVo1Odt4pHYLz4RKdG9kEffVdp-j9cfm2WKXrl6fnxXydKprjmDJTzyTWfFYbTktWYVyRos4rCYwTUhJJuJkZSnABSnLGmSTKUGXqsihlzjmdopsh90M2YuftVvqjcNKK1Xwt-h2GgpeY4AN02rtBq7wLwWsjlI2nP6KXthGARc9ObMTATvTsBECX0ZvzX-afa__Y7geb7iAcrPYiKKtbpWvrtYqidvbvgC9Le43u |
| CitedBy_id | crossref_primary_10_1109_LES_2018_2812784 crossref_primary_10_1016_j_sysarc_2024_103080 crossref_primary_10_1109_TAI_2023_3308099 |
| Cites_doi | 10.1109/TVLSI.2010.2090543 10.1109/TCAD.2006.883915 10.1109/TCAD.2005.855950 10.1016/j.sysarc.2010.04.004 10.1109/4235.585892 10.1145/69558.75700 10.1016/j.jda.2008.07.008 10.1145/968280.968307 10.1145/605440.605446 10.1016/j.micpro.2014.09.001 10.1145/1011528.1011529 10.1109/3477.484436 10.1109/TCAD.2014.2387375 10.1016/j.vlsi.2009.06.002 10.1109/TVLSI.2008.2001863 |
| ContentType | Journal Article |
| Copyright | 2016 Elsevier B.V. Distributed under a Creative Commons Attribution 4.0 International License |
| Copyright_xml | – notice: 2016 Elsevier B.V. – notice: Distributed under a Creative Commons Attribution 4.0 International License |
| DBID | AAYXX CITATION 1XC |
| DOI | 10.1016/j.sysarc.2016.11.011 |
| DatabaseName | CrossRef Hyper Article en Ligne (HAL) |
| DatabaseTitle | CrossRef |
| DatabaseTitleList | |
| DeliveryMethod | fulltext_linktorsrc |
| Discipline | Computer Science |
| EISSN | 1873-6165 |
| EndPage | 159 |
| ExternalDocumentID | oai:HAL:hal-01587020v1 10_1016_j_sysarc_2016_11_011 S1383762116302193 |
| GroupedDBID | --K --M -~X .DC .~1 0R~ 1B1 1~. 1~5 29L 4.4 457 4G. 5GY 5VS 7-5 71M 8P~ AACTN AAEDT AAEDW AAIAV AAIKJ AAKOC AALRI AAOAW AAQFI AAQXK AAXUO AAYFN ABBOA ABFNM ABFRF ABJNI ABMAC ABXDB ABYKQ ACDAQ ACGFO ACGFS ACNNM ACRLP ACZNC ADBBV ADEZE ADJOM ADMUD ADTZH AEBSH AECPX AEFWE AEKER AENEX AFKWA AFTJW AGHFR AGUBO AGYEJ AHJVU AHZHX AIALX AIEXJ AIKHN AITUG AJBFU AJOXV ALMA_UNASSIGNED_HOLDINGS AMFUW AMRAJ AOUOD ASPBG AVWKF AXJTR AZFZN BJAXD BKOJK BKOMP BLXMC CS3 DU5 EBS EFJIC EFLBG EJD EO8 EO9 EP2 EP3 FDB FEDTE FGOYB FIRID FNPLU FYGXN G-Q GBLVA GBOLZ HVGLF HZ~ IHE J1W JJJVA KOM M41 MO0 MS~ N9A O-L O9- OAUVE OZT P-8 P-9 P2P PC. PQQKQ Q38 R2- RIG ROL RPZ RXW SBC SDF SDG SDP SES SEW SPC SPCBC SST SSV SSZ T5K TAE TN5 U5U UHS ~G- 9DU AATTM AAXKI AAYWO AAYXX ABWVN ACLOT ACRPL ACVFH ADCNI ADNMO AEIPS AEUPX AFJKZ AFPUW AGQPQ AIGII AIIUN AKBMS AKRWK AKYEP ANKPU APXCP CITATION EFKBS ~HD 1XC |
| ID | FETCH-LOGICAL-c340t-6fd9a0e89df8376b00b25d4ba1682272a28f9f32051ca8686a2cf3cfd757a4883 |
| ISICitedReferencesCount | 4 |
| ISICitedReferencesURI | http://www.webofscience.com/api/gateway?GWVersion=2&SrcApp=Summon&SrcAuth=ProQuest&DestLinkType=CitingArticles&DestApp=WOS_CPL&KeyUT=000403636900012&url=https%3A%2F%2Fcvtisr.summon.serialssolutions.com%2F%23%21%2Fsearch%3Fho%3Df%26include.ft.matches%3Dt%26l%3Dnull%26q%3D |
| ISSN | 1383-7621 |
| IngestDate | Tue Oct 14 20:38:21 EDT 2025 Sat Nov 29 01:35:54 EST 2025 Tue Nov 18 21:01:45 EST 2025 Fri Feb 23 02:28:00 EST 2024 |
| IsPeerReviewed | true |
| IsScholarly | true |
| Keywords | Subgraph enumeration algorithm Custom instruction Parallel algorithms Subgraph selection algorithm Extensible processors |
| Language | English |
| License | Distributed under a Creative Commons Attribution 4.0 International License: http://creativecommons.org/licenses/by/4.0 |
| LinkModel | OpenURL |
| MergedId | FETCHMERGED-LOGICAL-c340t-6fd9a0e89df8376b00b25d4ba1682272a28f9f32051ca8686a2cf3cfd757a4883 |
| ORCID | 0000-0001-7216-749X |
| PageCount | 11 |
| ParticipantIDs | hal_primary_oai_HAL_hal_01587020v1 crossref_citationtrail_10_1016_j_sysarc_2016_11_011 crossref_primary_10_1016_j_sysarc_2016_11_011 elsevier_sciencedirect_doi_10_1016_j_sysarc_2016_11_011 |
| PublicationCentury | 2000 |
| PublicationDate | 2017-05-01 |
| PublicationDateYYYYMMDD | 2017-05-01 |
| PublicationDate_xml | – month: 05 year: 2017 text: 2017-05-01 day: 01 |
| PublicationDecade | 2010 |
| PublicationTitle | Journal of systems architecture |
| PublicationYear | 2017 |
| Publisher | Elsevier B.V Elsevier |
| Publisher_xml | – name: Elsevier B.V – name: Elsevier |
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| SSID | ssj0005512 |
| Score | 2.116539 |
| Snippet | With the ability of customization for an application domain, extensible processors have been used more and more in embedded systems in recent years. Extensible... |
| SourceID | hal crossref elsevier |
| SourceType | Open Access Repository Enrichment Source Index Database Publisher |
| StartPage | 149 |
| SubjectTerms | Computer Science Custom instruction Extensible processors Hardware Architecture Parallel algorithms Subgraph enumeration algorithm Subgraph selection algorithm |
| Title | Parallel custom instruction identification for extensible processors |
| URI | https://dx.doi.org/10.1016/j.sysarc.2016.11.011 https://inria.hal.science/hal-01587020 |
| Volume | 76 |
| WOSCitedRecordID | wos000403636900012&url=https%3A%2F%2Fcvtisr.summon.serialssolutions.com%2F%23%21%2Fsearch%3Fho%3Df%26include.ft.matches%3Dt%26l%3Dnull%26q%3D |
| hasFullText | 1 |
| inHoldings | 1 |
| isFullTextHit | |
| isPrint | |
| journalDatabaseRights | – providerCode: PRVESC databaseName: ScienceDirect customDbUrl: eissn: 1873-6165 dateEnd: 99991231 omitProxy: false ssIdentifier: ssj0005512 issn: 1383-7621 databaseCode: AIEXJ dateStart: 19960101 isFulltext: true titleUrlDefault: https://www.sciencedirect.com providerName: Elsevier |
| link | http://cvtisr.summon.serialssolutions.com/2.0.0/link/0/eLvHCXMwtV1bb9owGLVYu4e97D61uyma9oZSEYfEySOiVHSrENI6iTfLceIBCqFqC-Jn7CfvxHYuCE3tHvYSkJNA7O_ku_n4MyFfRSqpigV1Q3y4fcZCV_ixZgIwiYgkSGiiN5tgk0k0m8XTTud3tRZmm7OiiHa7-Oa_ihptEHa5dPYfxF3_KBrwHULHEWLH8VGCn4rbcn-UvDvcwLFbaTqArRHbNctylc3TaYrhaKc57OUCKrtoYG0neA5dVlP2-a7bnn2oJDZbCJN1nWfFr3xtDaJO1duM9BxWcd6iAC02muAniuWmbhzCl8-EPjFarUSxsYx-m5eAratZgCZZZi17S7ciGHahe7228mVt7emZ6qXWEHumVPiBjjfphuUZ-ozuluy88KwsxGqV9l5J7fHgB5-eX_Cry8n3_bMtHuJ4cIXjXOR4_gD6i_a2iKePKQtiqPrjweVo9q2hDQVmBr3qTLUcU3MGDx_pb-7Ok3mVuNeOzPVL8tyK0xkY5Lwinax4TV5Uu3s4Vtm_IecVkBwDJKcFJGcfSA6A5DRAchogvSU_L0bXw7Fr99xwpd_v3buhSmPRy6I4VRFsD5RyQoO0nwgvhCvJqKCRipVPoculiMIoFFQqX6qUBUzAGPjvyFGxLrIT4giYUcS_QgmFmBtvfi9DuJGFiefLqC_ZKfGroeHSFqQv90XJecU8XHIzoLwcUMSqHAN6Stz6rhtTkOWB61k16tw6lcZZ5MDTA3d-gZDqPynrsAMpvGxrcPL-MRd9IM-aN-QjOYKwsk_kqdzeL-5uP1uE_QH756S2 |
| linkProvider | Elsevier |
| openUrl | ctx_ver=Z39.88-2004&ctx_enc=info%3Aofi%2Fenc%3AUTF-8&rfr_id=info%3Asid%2Fsummon.serialssolutions.com&rft_val_fmt=info%3Aofi%2Ffmt%3Akev%3Amtx%3Ajournal&rft.genre=article&rft.atitle=Parallel+Custom+Instruction+Identification+for+Extensible+Processors&rft.jtitle=Journal+of+systems+architecture&rft.au=Xiao%2C+Chenglong&rft.au=Wang%2C+Shanshan&rft.au=Liu%2C+Wanjun&rft.au=Casseau%2C+Emmanuel&rft.date=2017-05-01&rft.pub=Elsevier&rft.issn=1383-7621&rft.volume=76&rft.spage=149&rft.epage=159&rft_id=info:doi/10.1016%2Fj.sysarc.2016.11.011&rft.externalDBID=HAS_PDF_LINK&rft.externalDocID=oai%3AHAL%3Ahal-01587020v1 |
| thumbnail_l | http://covers-cdn.summon.serialssolutions.com/index.aspx?isbn=/lc.gif&issn=1383-7621&client=summon |
| thumbnail_m | http://covers-cdn.summon.serialssolutions.com/index.aspx?isbn=/mc.gif&issn=1383-7621&client=summon |
| thumbnail_s | http://covers-cdn.summon.serialssolutions.com/index.aspx?isbn=/sc.gif&issn=1383-7621&client=summon |