APA (7th ed.) Citation

Xiao, C., Wang, S., Liu, W., & Casseau, E. (2017). Parallel custom instruction identification for extensible processors. Journal of systems architecture, 76, 149-159. https://doi.org/10.1016/j.sysarc.2016.11.011

Chicago Style (17th ed.) Citation

Xiao, Chenglong, Shanshan Wang, Wanjun Liu, and Emmanuel Casseau. "Parallel Custom Instruction Identification for Extensible Processors." Journal of Systems Architecture 76 (2017): 149-159. https://doi.org/10.1016/j.sysarc.2016.11.011.

MLA (9th ed.) Citation

Xiao, Chenglong, et al. "Parallel Custom Instruction Identification for Extensible Processors." Journal of Systems Architecture, vol. 76, 2017, pp. 149-159, https://doi.org/10.1016/j.sysarc.2016.11.011.