Xiao, C., Wang, S., Liu, W., & Casseau, E. (2017). Parallel custom instruction identification for extensible processors. Journal of systems architecture, 76, 149-159. https://doi.org/10.1016/j.sysarc.2016.11.011
Citace podle Chicago (17th ed.)Xiao, Chenglong, Shanshan Wang, Wanjun Liu, a Emmanuel Casseau. "Parallel Custom Instruction Identification for Extensible Processors." Journal of Systems Architecture 76 (2017): 149-159. https://doi.org/10.1016/j.sysarc.2016.11.011.
Citace podle MLA (9th ed.)Xiao, Chenglong, et al. "Parallel Custom Instruction Identification for Extensible Processors." Journal of Systems Architecture, vol. 76, 2017, pp. 149-159, https://doi.org/10.1016/j.sysarc.2016.11.011.
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