A Secure JTAG Wrapper for SoC Testing and Debugging

IEEE Std. 1149.1, also known as the Joint Test Access Group (JTAG) standard, provides excellent controllability and observability for ICs and hence is widely used in IC testing, debugging, failure analysis, or even online chip control/monitoring. Unfortunately, it has also become a backdoor for atta...

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Veröffentlicht in:	IEEE access Jg. 10; S. 37603 - 37612
Hauptverfasser:	Lee, Kuen-Jong, Lu, Zheng-Yao, Yeh, Shih-Chun
Format:	Journal Article
Sprache:	Englisch
Veröffentlicht:	Piscataway IEEE 2022 The Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Schlagworte:	Authentication Debugging Encryption Failure analysis Generators Hardware security IEEE test standard security in-field debugging in-field testing Integrated circuits JTAG security memory attack Microprocessors Observability (systems) Physical unclonable function physical unclonable function (PUF) Registers RISC secure JTAG wrapper Testing
ISSN:	2169-3536, 2169-3536
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Abstract	IEEE Std. 1149.1, also known as the Joint Test Access Group (JTAG) standard, provides excellent controllability and observability for ICs and hence is widely used in IC testing, debugging, failure analysis, or even online chip control/monitoring. Unfortunately, it has also become a backdoor for attackers to manipulate the ICs or grab confidential information from the ICs. One way to address this problem is to disable JTAG pins after manufacturing testing. However this countermeasure prohibits the in-filed testing and debugging capability. Other countermeasures such as authentication and encryption/decryption methods based on specific static keys have also been proposed. However, these approaches may suffer from side-channel or memory attacks that may figure out the specific keys. This paper presents an authentication-based secure JTAG wrapper with a dynamic feature to defend against the attacks mentioned above. We generate different keys for different test data dynamically. Therefore, only legal test data can be updated to the test data registers (TDRs) through JTAG. Furthermore, the attackers will get fake responses if they shift in illegal test data, which makes it extremely difficult to break our proposed method. We can also employ the physical unclonable function (PUF) to distinguish the legal test data for different chips. Experiments on a RISC-V CPU processor called SCR1 show that our proposed method can have an area overhead of only 0.49%.
AbstractList	IEEE Std. 1149.1, also known as the Joint Test Access Group (JTAG) standard, provides excellent controllability and observability for ICs and hence is widely used in IC testing, debugging, failure analysis, or even online chip control/monitoring. Unfortunately, it has also become a backdoor for attackers to manipulate the ICs or grab confidential information from the ICs. One way to address this problem is to disable JTAG pins after manufacturing testing. However this countermeasure prohibits the in-filed testing and debugging capability. Other countermeasures such as authentication and encryption/decryption methods based on specific static keys have also been proposed. However, these approaches may suffer from side-channel or memory attacks that may figure out the specific keys. This paper presents an authentication-based secure JTAG wrapper with a dynamic feature to defend against the attacks mentioned above. We generate different keys for different test data dynamically. Therefore, only legal test data can be updated to the test data registers (TDRs) through JTAG. Furthermore, the attackers will get fake responses if they shift in illegal test data, which makes it extremely difficult to break our proposed method. We can also employ the physical unclonable function (PUF) to distinguish the legal test data for different chips. Experiments on a RISC-V CPU processor called SCR1 show that our proposed method can have an area overhead of only 0.49%.
Author	Yeh, Shih-Chun Lu, Zheng-Yao Lee, Kuen-Jong
Author_xml	– sequence: 1 givenname: Kuen-Jong orcidid: 0000-0002-6690-0074 surname: Lee fullname: Lee, Kuen-Jong email: kjlee@mail.ncku.edu.tw organization: Department of Electrical Engineering, National Cheng Kung University, Tainan, Taiwan – sequence: 2 givenname: Zheng-Yao surname: Lu fullname: Lu, Zheng-Yao organization: Department of Silicon Product Development, MediaTek Inc., Hsinchu, Taiwan – sequence: 3 givenname: Shih-Chun orcidid: 0000-0001-9608-6547 surname: Yeh fullname: Yeh, Shih-Chun organization: Department of Electrical Engineering, National Cheng Kung University, Tainan, Taiwan
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SubjectTerms	Authentication Debugging Encryption Failure analysis Generators Hardware security IEEE test standard security in-field debugging in-field testing Integrated circuits JTAG security memory attack Microprocessors Observability (systems) Physical unclonable function physical unclonable function (PUF) Registers RISC secure JTAG wrapper Testing
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Title	A Secure JTAG Wrapper for SoC Testing and Debugging
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