High-level area and power estimation for VLSI circuits

High-level power estimation, when given only a high-level design specification such as a functional or register-transfer level (RTL) description, requires high-level estimation of the circuit average activity and total capacitance. Considering that total capacitance is related to circuit area, this...

Ausführliche Beschreibung

Gespeichert in:
Bibliographische Detailangaben
Veröffentlicht in:IEEE transactions on computer-aided design of integrated circuits and systems Jg. 18; H. 6; S. 697 - 713
Hauptverfasser: Nemani, M., Najm, F.N.
Format: Journal Article
Sprache:Englisch
Veröffentlicht: New York, NY IEEE 01.06.1999
Institute of Electrical and Electronics Engineers
Schlagworte:
Applied sciences
Boolean functions
Capacitance
Circuits
Combinational circuits
Design automation
Design engineering
Design. Technologies. Operation analysis. Testing
Electronics
Equations
Estimates
Exact sciences and technology
Gates (circuits)
Integrated circuits
Libraries
Logic
Mathematical analysis
Mathematical models
Power dissipation
Registers
Semiconductor electronics. Microelectronics. Optoelectronics. Solid state devices
Switching circuits
Very large scale integration
Boolean equation
Area estimation
VLSI circuit
Complementary MOS technology
Power estimation
Integrated circuit
Complexity measure
Computer aided design
Implementation
ISSN:0278-0070
Online-Zugang:Volltext
Tags: Tag hinzufügen
Keine Tags, Fügen Sie den ersten Tag hinzu!
Beschreibung
Zusammenfassung:High-level power estimation, when given only a high-level design specification such as a functional or register-transfer level (RTL) description, requires high-level estimation of the circuit average activity and total capacitance. Considering that total capacitance is related to circuit area, this paper addresses the problem of computing the "area complexity" of multi-output combinational logic given only their functional description, i.e., Boolean equations, where area complexity refers to the number of gates required for an optimal multilevel implementation of the combinational logic. The proposed area model is based on transforming the multi-output Boolean function description into an equivalent single output function. The area model is empirical and results demonstrating its feasibility and utility are presented. Also, a methodology for converting the gate count estimates, obtained from the area model, into capacitance estimates is presented. High-level power estimates based on the total capacitance estimates and average activity estimates are also presented.
Bibliographie:ObjectType-Article-2
SourceType-Scholarly Journals-1
ObjectType-Feature-1
content type line 23
ISSN:0278-0070
DOI:10.1109/43.766722