Design of ternary encoder and decoder using CNTFET
Ternary logic emerges as an alternative to the conventional binary logic in designing high performance, energy-efficient VLSI circuits because it reduces the number of interconnects and chip area. In this paper, we presented low power and high speed 9:2 encoder and 2:9 decoder designs based on terna...
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| Published in: | International journal of electronics Vol. 109; no. 1; pp. 135 - 151 |
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| Main Authors: | , , |
| Format: | Journal Article |
| Language: | English |
| Published: |
Abingdon
Taylor & Francis
02.01.2022
Taylor & Francis LLC |
| Subjects: | |
| ISSN: | 0020-7217, 1362-3060 |
| Online Access: | Get full text |
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