Design of ternary encoder and decoder using CNTFET

Ternary logic emerges as an alternative to the conventional binary logic in designing high performance, energy-efficient VLSI circuits because it reduces the number of interconnects and chip area. In this paper, we presented low power and high speed 9:2 encoder and 2:9 decoder designs based on terna...

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Veröffentlicht in:International journal of electronics Jg. 109; H. 1; S. 135 - 151
Hauptverfasser: Prasad, Vikash, Banerjee, Anirban, Das, Debaprasad
Format: Journal Article
Sprache:Englisch
Veröffentlicht: Abingdon Taylor & Francis 02.01.2022
Taylor & Francis LLC
Schlagworte:
carbon nanotube field effect transistors
Carbon nanotubes
Chirality
Circuit design
Coders
Design
Field effect transistors
Integrated circuits
Logic
power delay product (PDP)
Semiconductor devices
ternary decoder
ternary encoder
Ternary logic
Threshold voltage
ISSN:0020-7217, 1362-3060
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Zusammenfassung:Ternary logic emerges as an alternative to the conventional binary logic in designing high performance, energy-efficient VLSI circuits because it reduces the number of interconnects and chip area. In this paper, we presented low power and high speed 9:2 encoder and 2:9 decoder designs based on ternary logic using carbon nanotube field effect transistors (CNTFETs). These circuits have been extensively simulated at 32 nm CNTFET technology at 0.9 V power supply voltage. The ternary decoder has a power delay product (PDP) of 24.62 aJ and the ternary encoder has a PDP of 133 aJ for a given load. In the proposed designs, the chirality of the carbon nanotube (CNT) is varied to control the threshold voltage. The designs have been analysed with process, voltage and temperature (PVT) variations and it is shown that with PVT variations the performance of the designs vary marginally.
Bibliographie:ObjectType-Article-1
SourceType-Scholarly Journals-1
ObjectType-Feature-2
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ISSN:0020-7217
1362-3060
DOI:10.1080/00207217.2021.1908620