Heuristic Logic Resynthesis Algorithms at the Core of Peephole Optimization

Logic resynthesis is one of the core problems in modern peephole logic optimization algorithms. Given a target function and a set of existing functions, logic resynthesis asks for a circuit reusing some of the existing functions and generating the target. While exact methods such as enumeration and...

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Vydané v:IEEE transactions on computer-aided design of integrated circuits and systems Ročník 42; číslo 11; s. 1
Hlavní autori: Lee, Siang-Yun, Micheli, Giovanni De
Médium: Journal Article
Jazyk:English
Vydavateľské údaje: New York IEEE 01.11.2023
The Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Predmet:
Algorithms
Boolean resubstitution
Circuits
combinational circuit
Enumeration
Heuristic
Heuristic algorithms
Integrated circuit modeling
Inverters
Logic
Logic gates
Logic synthesis
Multiplexing
Optimization
peephole optimization
resynthesis
Wires
ISSN:0278-0070, 1937-4151
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Popis
Shrnutí:Logic resynthesis is one of the core problems in modern peephole logic optimization algorithms. Given a target function and a set of existing functions, logic resynthesis asks for a circuit reusing some of the existing functions and generating the target. While exact methods such as enumeration and SATbased synthesis guarantee optimal solutions, limitations on the problem size are inevitable due to scalability concerns. In this work, we propose heuristic resynthesis algorithms for ANDbased, majority-based, and multiplexer-based circuits, which are scalable in all aspects. Used as the core of high-effort optimization, our heuristic resynthesis algorithms play a key role in enabling 2-3% further size reduction on benchmarks that are already processed by state-of-the-art optimization flows.
Bibliografia:ObjectType-Article-1
SourceType-Scholarly Journals-1
ObjectType-Feature-2
content type line 14
ISSN:0278-0070
1937-4151
DOI:10.1109/TCAD.2023.3256341