Analog-Domain Self-Interference Cancellation for Practical Multi-Tap Full-Duplex System: Theory, Modeling, and Algorithm

Practical, in-band, full-duplex (IBFD) systems typically require more than 100 dB of self-interference cancellation (SIC). Digital processing alone is insufficient for achieving this target, which drives us towards supplementary analog mitigation techniques. We propose an analog-domain, self-interfe...

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Veröffentlicht in:IEEE journal on selected areas in communications Jg. 41; H. 9; S. 1
Hauptverfasser: Morgenstern, Carl W., Rong, Yu, Herschfelt, Andrew, Molnar, Alyosha C., Apsel, Alyssa B., Landon, David G., Bliss, Daniel W.
Format: Journal Article
Sprache:Englisch
Veröffentlicht: New York IEEE 01.09.2023
The Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Schlagworte:
Algorithms
Analog circuits
Cancellation
Cancellation circuits
Carrier frequencies
Codes
Delay effects
Delays
Design parameters
Full-duplex
Hardware
Integrated circuit modeling
Interference
Interference cancellation
Optimization
outer hull
Quantization (signal)
self-interference cancellation
Systems design
wireless communications
ISSN:0733-8716, 1558-0008
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Zusammenfassung:Practical, in-band, full-duplex (IBFD) systems typically require more than 100 dB of self-interference cancellation (SIC). Digital processing alone is insufficient for achieving this target, which drives us towards supplementary analog mitigation techniques. We propose an analog-domain, self-interference cancellation circuit to enable pass-band, analog SIC in an IBFD system. Analog SIC is limited by several hardware constraints and design choices, including finite tap-delay resolution, non-negative tap constraints, and bit precision quantization. We characterize the performance impact of each of these limitations as a function of signal bandwidth, carrier frequency, bit precision, and other system design parameters. We further characterize the achievable system performance under all of these limitations combined. We simulate several realistic examples to illustrate the relationship between the achievable self-mitigation performance and various system design choices. We implement a simple constrained optimization algorithm informed by these results to optimize the tap-delay weights of the analog circuit under these system constraints. We simulate the achievable mitigation performance and demonstrate as much as 45 dB of analog-domain, self-interference mitigation of a wide-band signal with realistic system configurations.
Bibliographie:ObjectType-Article-1
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ISSN:0733-8716
1558-0008
DOI:10.1109/JSAC.2023.3287608