Statistical BER Analysis of Wireline Links With Non-Binary Linear Block Codes Subject to DFE Error Propagation

This paper presents a statistical model to accurately estimate post-FEC BER for high-speed wireline links using standard linear block codes, such as the RS(544,514,15) KP4 and RS(528,514,7) KR4 codes. A hierarchical approach is adopted to analyze the propagation of PAM-symbol and FEC-symbol errors t...

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Vydané v:IEEE transactions on circuits and systems. I, Regular papers Ročník 67; číslo 1; s. 284 - 297
Hlavní autori: Yang, Ming, Shahramian, Shayan, Shakiba, Hossein, Wong, Henry, Krotnev, Peter, Carusone, Anthony Chan
Médium: Journal Article
Jazyk:English
Vydavateľské údaje: New York IEEE 01.01.2020
The Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Predmet:
Agglomeration
BER estimation
Binary codes
Block codes
burst error
Communications systems
Computational modeling
decision feedback equalization (DFE)
Decision feedback equalizers
Dynamic programming
error propagation
Estimation
Forward error correction
forward error correction (FEC)
linear block code
Markov chains
Markov model
Markov processes
Propagation
pulse amplitude modulation (PAM)
state aggregation
State reduction
Statistical models
Test vehicles
time aggregation
Transceivers
wireline channel
ISSN:1549-8328, 1558-0806
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Shrnutí:This paper presents a statistical model to accurately estimate post-FEC BER for high-speed wireline links using standard linear block codes, such as the RS(544,514,15) KP4 and RS(528,514,7) KR4 codes. A hierarchical approach is adopted to analyze the propagation of PAM-symbol and FEC-symbol errors through a two-layer Markov model. A series of techniques including state aggregation, time aggregation, state reduction, and dynamic programming are introduced making the time complexity to compute post-FEC BER below 10 -15 reasonable. Error bounds associated with each method are found. The efficiency of the proposed model allows it to handle a larger state space, more DFE taps, and more sophisticated linear block codes than prior work. A 4-PAM 60 Gb/s wireline transceiver fabricated in a 7 nm FinFET technology is used as a test vehicle to validate this model. Measured data with two different channels reveals that the statistical model can properly predict the post-FEC error floor with standard FEC codes. While this paper demonstrates the method for capturing DFE error propagation, the method is general and can be applied to model other communication systems having memory effects. Moreover, our proposed model can be easily extended to higher-level PAM schemes and other advanced equalizer architectures to assist in making architectural choices for wireline transceivers.
Bibliografia:ObjectType-Article-1
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content type line 14
ISSN:1549-8328
1558-0806
DOI:10.1109/TCSI.2019.2943569