Multiplicative and additive parallel multigrid algorithms for the acceleration of compressible flow computations on unstructured meshes

In this paper we examine how parallel multigrid acceleration can be used to improve the efficiency of two-dimensional compressible steady flow calculations on unstructured meshes. We study two parallel multigrid formulations. The first one is based on the standard approach that relies on domain part...

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Bibliographic Details
Published in:Applied numerical mathematics Vol. 36; no. 4; pp. 401 - 426
Main Authors: Fournier, L., Lanteri, S.
Format: Journal Article
Language:English
Published: Amsterdam Elsevier B.V 01.03.2001
Elsevier
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ISSN:0168-9274, 1873-5460
Online Access:Get full text
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Summary:In this paper we examine how parallel multigrid acceleration can be used to improve the efficiency of two-dimensional compressible steady flow calculations on unstructured meshes. We study two parallel multigrid formulations. The first one is based on the standard approach that relies on domain partitioning for the parallel treatment of the pre- and post-smoothing steps whereas the coarse grid levels are visited sequentially according to predefined cycles (V-cycle, F-cycle or W-cycle). Reducing communication overheads is of crucial importance for parallel multigrid methods. When adopting the standard parallelization technique (i.e., intra-level parallelism based on domain partitioning) the usual drawback is that, as the calculation in a given cycling strategy proceeds from the finest level to the coarsest ones, the ratio between communication and calculation becomes worse resulting in a notable degradation of the parallel efficiency. In order to improve this situation, the second formulation considered in this study makes use of residual and correction filtering techniques allowing a parallel treatment of the various grid levels. This leads to the notion of inter-level parallelism. We propose distributed memory parallel versions of these two multigrid formulations and evaluate them through numerical experiments that are performed on a cluster of Pentium Pro computers interconnected via a 100 Mbit/s FastEthernet switch.
ISSN:0168-9274
1873-5460
DOI:10.1016/S0168-9274(00)00017-9