Shared-Semaphored Cache Implementation for Parallel Program Execution in Multi-Core Systems

The paper brings forward an idea of multi-threaded computation synchronization based on the shared semaphored cache in the multi-core CPUs. It is dedicated to the implementation of multi-core PLC control, embedded solution or parallel computation of models described using hardware description langua...

Celý popis

Uložené v:
Podrobná bibliografia
Vydané v:International Journal of Electronics and Telecommunications Ročník 69; číslo 2; s. 371 - 382
Hlavní autori: Milik, Adam, Walichiewicz, Michał
Médium: Journal Article
Jazyk:English
Vydavateľské údaje: Warsaw Polish Academy of Sciences 01.01.2023
Predmet:
Algorithms
compiler
Computation
Computer memory
Control algorithms
Data exchange
Data processing
Hardware description languages
mapping
parallel execution
Parallel processing
Parallel programming
scheduling
Simulation
Synchronism
thread synchronization
Variables
ISSN:2300-1933, 2081-8491, 2300-1933
On-line prístup:Získať plný text
Tagy: Pridať tag
Žiadne tagy, Buďte prvý, kto otaguje tento záznam!
Popis
Shrnutí:The paper brings forward an idea of multi-threaded computation synchronization based on the shared semaphored cache in the multi-core CPUs. It is dedicated to the implementation of multi-core PLC control, embedded solution or parallel computation of models described using hardware description languages. The shared semaphored cache is implemented as guarded memory cells within a dedicated section of the cache memory that is shared by multiple cores. This enables the cores to speed up the data exchange and seamlessly synchronize the computation. The idea has been verified by creating a multi-core system model using Verilog HDL. The simulation of task synchronization methods allows for proving the benefits of shared semaphored memory cells over standard synchronization methods. The proposed idea enhances the computation in the algorithms that consist of relatively short tasks that can be processed in parallel and requires fast synchronization mechanisms to avoid data race conditions.
Bibliografia:ObjectType-Article-1
SourceType-Scholarly Journals-1
ObjectType-Feature-2
content type line 14
ISSN:2300-1933
2081-8491
2300-1933
DOI:10.24425/ijet.2023.144373