Design and implementation of Least Mean Square adaptive FIR filter using offset binary coding based Distributed Arithmetic

Distributed Arithmetic (DA) based architecture is an efficient technique to attain high throughput without hardware multiplier and also it is essential for bit serial operation. The DA based Finite Impulse Response (FIR) adaptive filter is well suited for hardware implementation in Field Programmabl...

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Vydáno v:Microprocessors and microsystems Ročník 71; s. 102884
Hlavní autoři: Kalaiyarasi, D., Kalpalatha Reddy, T.
Médium: Journal Article
Jazyk:angličtina
Vydáno: Kidlington Elsevier B.V 01.11.2019
Elsevier BV
Témata:
Accumulators
Adaptive filter
Adaptive filters
Arithmetic
Arithmetic coding
Binary codes
Carry Save Accumulator
Distributed Arithmetic
Field programmable gate arrays
FIR filters
Hardware
Impulse response
Least Mean Square
Logic
Lookup tables
Offset binary coding
Reduction
Shift accumulator
Offset binary coding
Shift accumulator
Carry Save Accumulator
Adaptive filter
Distributed Arithmetic
Least Mean Square
ISSN:0141-9331
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Shrnutí:Distributed Arithmetic (DA) based architecture is an efficient technique to attain high throughput without hardware multiplier and also it is essential for bit serial operation. The DA based Finite Impulse Response (FIR) adaptive filter is well suited for hardware implementation in Field Programmable Gate Array (FPGA) device. In conventional DA the partial products of the filter coefficients have been pre-calculated and stored in Look up Table (LUT) which in turn will increase the logic elements and power. To overcome this problem DA based Least Mean Square (LMS) adaptive filter using offset binary coding (OBC) without LUT is proposed. The proposed method will reduce the logic elements by half when compared to the conventional DA based OBC filter. The Carry Save Accumulator (CSA) is used to carry out the operation of shift and accumulation. The proposed architecture is implemented in Quartus II 9.1 with the device as Stratix-EP2S15F484C3 which offers 13.72% high throughput, 56.92% reduction in logic elements, 42.84% reduction in power, 57.74% reduction in logical registers for N = 16 and for N = 32 the number of logical element is reduced to 80.87%, 66.66% reduction in power and 24.12% high throughput.
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ISSN:0141-9331
DOI:10.1016/j.micpro.2019.102884