Compact Modeling and Mitigation of Parasitics in Crosspoint Accelerators of Neural Networks

In-memory computing (IMC) can accelerate data-intensive tasks, such as matrix-vector multiplication (MVM) or artificial neural networks (ANNs) inference, by means of the crosspoint memory array, allowing to reduce time and energy consumption. IMC accuracy, however, is affected by nonidealities, such...

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Bibliographic Details
Published in:IEEE transactions on electron devices Vol. 71; no. 3; pp. 1 - 7
Main Authors: Lepri, N., Glukhov, A., Mannocci, P., Porzani, M., Ielmini, D.
Format: Journal Article
Language:English
Published: New York IEEE 01.03.2024
The Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subjects:
Accuracy
Arrays
Artificial neural networks
Deep learning
emerging memory technologies
Energy consumption
hardware accelerator
in-memory computing (IMC)
Logic gates
Mathematical analysis
Matrix algebra
Microprocessors
Programming
Resistance
resistive switching memory (RRAM)
Transistors
Voltage
Wires
ISSN:0018-9383, 1557-9646
Online Access:Get full text
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Summary:In-memory computing (IMC) can accelerate data-intensive tasks, such as matrix-vector multiplication (MVM) or artificial neural networks (ANNs) inference, by means of the crosspoint memory array, allowing to reduce time and energy consumption. IMC accuracy, however, is affected by nonidealities, such as variability of the conductive weights or IR drop along wires due to parasitic resistances, whose impact steeply increases with the increase of array size. This work proposes a compact model to assess the impact of nonidealities for various circuital implementations, together with architectural schemes for their mitigation based on replicated arrays. The proposed mitigation techniques allow to restore the ANN accuracy from 72.7% to 94.9%, close to the software accuracy of 96.9%, in view of an increased area and energy consumption.
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ISSN:0018-9383
1557-9646
DOI:10.1109/TED.2024.3360015