FPGA based fast and high-throughput 2-slow retiming 128-bit AES encryption algorithm

This paper presents a high throughput digital design of the 128-bit Advanced Encryption Standard (AES) algorithm based on the 2-slow retiming technique on FPGA. The C-slow retiming is a well-known optimization and high performance technique. It can enhance designs with feedback loops and automatical...

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Bibliographic Details
Published in:	Microelectronics Vol. 45; no. 8; pp. 1014 - 1025
Main Authors:	Farashahi, Reza Rezaeian, Rashidi, Bahram, Sayedi, Sayed Masoud
Format:	Journal Article
Language:	English
Published:	Elsevier Ltd 01.08.2014
Subjects:	AES Algorithms Architecture C-Slow retiming Combinational logic circuits Constants Encryption Field programmable gate arrays High-throughput Optimization Pipelining Registers Transformations High-throughput C-Slow retiming Pipelining Combinational logic circuits AES
ISSN:	1879-2391, 0026-2692
Online Access:	Get full text
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