FPGA based fast and high-throughput 2-slow retiming 128-bit AES encryption algorithm
This paper presents a high throughput digital design of the 128-bit Advanced Encryption Standard (AES) algorithm based on the 2-slow retiming technique on FPGA. The C-slow retiming is a well-known optimization and high performance technique. It can enhance designs with feedback loops and automatical...
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| Veröffentlicht in: | Microelectronics Jg. 45; H. 8; S. 1014 - 1025 |
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01.08.2014
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| Abstract | This paper presents a high throughput digital design of the 128-bit Advanced Encryption Standard (AES) algorithm based on the 2-slow retiming technique on FPGA. The C-slow retiming is a well-known optimization and high performance technique. It can enhance designs with feedback loops and automatically rebalances the registers in the design. The C-slow retiming can break the critical path of the design into finer pieces to improve the throughput of the design. The complexity of the C-slow retiming on FPGA is to find the best register allocation in the data path of the design so that by increasing the number of registers, relocation of the registers to balance the AES architecture be in the best mode, and the critical path be optimally pipelined and improved. In this paper, architecture of the AES algorithm is implemented in the gate level by high-speed and breakable structures that are desirable for the 2-slow retiming. The Mix-columns transformation is implemented based on multiplication by constants 2 and 3 modules with combinational logic circuits. This work has been successfully verified and synthesized using Xilinx ISE 11 byVirtex-5, XC5VLX85 FPGA. The proposed implementation achieves a high throughput of 86Gb/s and high maximum operation frequency of 671.524MHz whereas the highest throughput and the highest operation frequency reported in the literature are 73.737Gb/s and 576.07MHz, respectively. |
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| AbstractList | This paper presents a high throughput digital design of the 128-bit Advanced Encryption Standard (AES) algorithm based on the 2-slow retiming technique on FPGA. The C-slow retiming is a well-known optimization and high performance technique. It can enhance designs with feedback loops and automatically rebalances the registers in the design. The C-slow retiming can break the critical path of the design into finer pieces to improve the throughput of the design. The complexity of the C-slow retiming on FPGA is to find the best register allocation in the data path of the design so that by increasing the number of registers, relocation of the registers to balance the AES architecture be in the best mode, and the critical path be optimally pipelined and improved. In this paper, architecture of the AES algorithm is implemented in the gate level by high-speed and breakable structures that are desirable for the 2-slow retiming. The Mix-columns transformation is implemented based on multiplication by constants 2 and 3 modules with combinational logic circuits. This work has been successfully verified and synthesized using Xilinx ISE 11 byVirtex-5, XC5VLX85 FPGA. The proposed implementation achieves a high throughput of 86 Gb/s and high maximum operation frequency of 671.524 MHz whereas the highest throughput and the highest operation frequency reported in the literature are 73.737 Gb/s and 576.07 MHz, respectively. This paper presents a high throughput digital design of the 128-bit Advanced Encryption Standard (AES) algorithm based on the 2-slow retiming technique on FPGA. The C-slow retiming is a well-known optimization and high performance technique. It can enhance designs with feedback loops and automatically rebalances the registers in the design. The C-slow retiming can break the critical path of the design into finer pieces to improve the throughput of the design. The complexity of the C-slow retiming on FPGA is to find the best register allocation in the data path of the design so that by increasing the number of registers, relocation of the registers to balance the AES architecture be in the best mode, and the critical path be optimally pipelined and improved. In this paper, architecture of the AES algorithm is implemented in the gate level by high-speed and breakable structures that are desirable for the 2-slow retiming. The Mix-columns transformation is implemented based on multiplication by constants 2 and 3 modules with combinational logic circuits. This work has been successfully verified and synthesized using Xilinx ISE 11 byVirtex-5, XC5VLX85 FPGA. The proposed implementation achieves a high throughput of 86Gb/s and high maximum operation frequency of 671.524MHz whereas the highest throughput and the highest operation frequency reported in the literature are 73.737Gb/s and 576.07MHz, respectively. |
| Author | Farashahi, Reza Rezaeian Rashidi, Bahram Sayedi, Sayed Masoud |
| Author_xml | – sequence: 1 givenname: Reza Rezaeian surname: Farashahi fullname: Farashahi, Reza Rezaeian email: farashahi@cc.iut.ac.ir organization: Department of Mathematics, Isfahan University of Technology, Isfahan 84156-83111, Iran – sequence: 2 givenname: Bahram surname: Rashidi fullname: Rashidi, Bahram email: b.rashidi@ec.iut.ac.ir, b_rashidi86@yahoo.com organization: Department of Electrical & Computer Engineering, Isfahan University of Technology, Isfahan 84156-83111, Iran – sequence: 3 givenname: Sayed Masoud surname: Sayedi fullname: Sayedi, Sayed Masoud email: m_sayedi@cc.iut.ac.ir organization: Department of Electrical & Computer Engineering, Isfahan University of Technology, Isfahan 84156-83111, Iran |
| BookMark | eNp9kD1PwzAQhj0UibbwB5g8siT4Kx-VWKqqLUiVQKLMlmM7iaMkDrYL6r8nUZkYOp1OuufuvWcBZr3tNQAPGMUY4fSpiTvd2JggzGKUxAixGZjjPFtFhK7wLVh43yCEkoywOTju3vdrWAivFSyFD1D0CtamqqNQO3uq6uEUIIl8a3-g08F0pq8gJnlUmADX2w-oe-nOQzC2h6KtrDOh7u7ATSlar-__6hJ87rbHzUt0eNu_btaHSFJKQ1SkK5SN8ZDEslQpwaliOqOMlAVlScFyLbBQtGRq7JKCUFywTLASJwJRIgq6BI-XvYOzXyftA--Ml7ptRa_tyXOcpNl4AWf5OJpfRqWz3jtdcmmCmGIHJ0zLMeKTPN7wSR6f5HGU8DHdiJJ_6OBMJ9z5OvR8gfT4_7fRjntpRldaGadl4Mqaa_gvXuSLow |
| CitedBy_id | crossref_primary_10_1002_cpe_5287 crossref_primary_10_1364_JOCN_439677 crossref_primary_10_1016_j_jisa_2018_01_001 crossref_primary_10_1016_j_vlsi_2023_102057 crossref_primary_10_3390_electronics10162023 crossref_primary_10_1049_iet_cdt_2019_0157 crossref_primary_10_1049_iet_cdt_2019_0179 crossref_primary_10_1109_TPDS_2015_2407896 crossref_primary_10_1080_00051144_2020_1816388 crossref_primary_10_1007_s10470_020_01691_0 crossref_primary_10_1016_j_micpro_2019_102972 crossref_primary_10_1002_cta_2832 crossref_primary_10_1007_s10470_021_01959_z crossref_primary_10_1007_s13369_017_2925_0 crossref_primary_10_1016_j_ifacol_2018_07_172 crossref_primary_10_1007_s12652_020_02658_9 crossref_primary_10_1016_j_micpro_2015_07_005 crossref_primary_10_1186_s13677_020_00215_5 crossref_primary_10_3390_s21248347 crossref_primary_10_3390_computation7040063 crossref_primary_10_1016_j_jksuci_2016_01_004 crossref_primary_10_1002_cta_2645 crossref_primary_10_1049_iet_cds_2018_5457 crossref_primary_10_1016_j_mejo_2019_06_012 crossref_primary_10_1155_2018_4804729 crossref_primary_10_1002_spy2_254 crossref_primary_10_1016_j_mejo_2021_105085 crossref_primary_10_1117_1_JEI_32_1_013012 crossref_primary_10_1007_s11277_016_3385_7 crossref_primary_10_4018_IJERTCS_2020070105 crossref_primary_10_1002_cta_4264 crossref_primary_10_1002_spy2_292 crossref_primary_10_1109_ACCESS_2025_3570727 |
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| ContentType | Journal Article |
| Copyright | 2014 Elsevier Ltd |
| Copyright_xml | – notice: 2014 Elsevier Ltd |
| DBID | AAYXX CITATION 7SP 8FD L7M |
| DOI | 10.1016/j.mejo.2014.05.004 |
| DatabaseName | CrossRef Electronics & Communications Abstracts Technology Research Database Advanced Technologies Database with Aerospace |
| DatabaseTitle | CrossRef Technology Research Database Advanced Technologies Database with Aerospace Electronics & Communications Abstracts |
| DatabaseTitleList | Technology Research Database |
| DeliveryMethod | fulltext_linktorsrc |
| Discipline | Engineering Architecture |
| EndPage | 1025 |
| ExternalDocumentID | 10_1016_j_mejo_2014_05_004 S0026269214001505 |
| GroupedDBID | --K --M .~1 0R~ 123 1B1 1~. 1~5 29M 4.4 457 4G. 5VS 7-5 71M 8P~ 9JN AABNK AABXZ AACTN AAEDT AAEDW AAEPC AAIKJ AAKOC AALRI AAOAW AAQFI AAXKI AAXUO AAYFN ABBOA ABDPE ABFNM ABJNI ABMAC ABTAH ABXDB ABXRA ACDAQ ACNNM ACRLP ACZNC ADBBV ADEZE ADJOM ADTZH AEBSH AECPX AEIPS AEKER AENEX AEZYN AFJKZ AFRZQ AFTJW AGHFR AGUBO AGYEJ AHHHB AHJVU AHZHX AIALX AIEXJ AIKHN AITUG AKRWK ALMA_UNASSIGNED_HOLDINGS AMRAJ ANKPU AOUOD ASPBG AVWKF AXJTR AZFZN BJAXD BKOJK BLXMC CS3 DU5 EBS EFJIC EJD EO8 EO9 EP2 EP3 F5P FDB FIRID FNPLU FYGXN G-2 G-Q GBLVA GBOLZ HZ~ IHE J1W JJJVA KOM LY7 M24 M41 MAGPM MO0 N9A O-L O9- OAUVE OZT P-8 P-9 P2P PC. Q38 RIG RNS ROL RPZ SDF SDG SDP SES SET SEW SMS SPC SPCBC SPD SSM SST SSV SSZ T5K WUQ XPP ZMT ZY4 ~G- 9DU AATTM AAYWO AAYXX ACLOT ACVFH ADCNI AEUPX AFPUW AIGII AIIUN AKBMS AKYEP APXCP CITATION EFKBS EFLBG ~HD 7SP 8FD L7M |
| ID | FETCH-LOGICAL-c333t-b69070040c1cfd6216d4e7342fb345b48ea1ad3f4d45b5b231b47a4f15a032ab3 |
| ISICitedReferencesCount | 51 |
| ISICitedReferencesURI | http://www.webofscience.com/api/gateway?GWVersion=2&SrcApp=Summon&SrcAuth=ProQuest&DestLinkType=CitingArticles&DestApp=WOS_CPL&KeyUT=000340219700004&url=https%3A%2F%2Fcvtisr.summon.serialssolutions.com%2F%23%21%2Fsearch%3Fho%3Df%26include.ft.matches%3Dt%26l%3Dnull%26q%3D |
| ISSN | 1879-2391 0026-2692 |
| IngestDate | Sun Sep 28 07:28:51 EDT 2025 Sat Nov 29 07:57:51 EST 2025 Tue Nov 18 22:13:47 EST 2025 Sat Mar 22 15:53:43 EDT 2025 |
| IsPeerReviewed | false |
| IsScholarly | false |
| Issue | 8 |
| Keywords | High-throughput C-Slow retiming Pipelining Combinational logic circuits AES |
| Language | English |
| LinkModel | OpenURL |
| MergedId | FETCHMERGED-LOGICAL-c333t-b69070040c1cfd6216d4e7342fb345b48ea1ad3f4d45b5b231b47a4f15a032ab3 |
| Notes | ObjectType-Article-2 SourceType-Scholarly Journals-1 ObjectType-Feature-1 content type line 23 |
| PQID | 1567070178 |
| PQPubID | 23500 |
| PageCount | 12 |
| ParticipantIDs | proquest_miscellaneous_1567070178 crossref_citationtrail_10_1016_j_mejo_2014_05_004 crossref_primary_10_1016_j_mejo_2014_05_004 elsevier_sciencedirect_doi_10_1016_j_mejo_2014_05_004 |
| PublicationCentury | 2000 |
| PublicationDate | 2014-08-01 |
| PublicationDateYYYYMMDD | 2014-08-01 |
| PublicationDate_xml | – month: 08 year: 2014 text: 2014-08-01 day: 01 |
| PublicationDecade | 2010 |
| PublicationTitle | Microelectronics |
| PublicationYear | 2014 |
| Publisher | Elsevier Ltd |
| Publisher_xml | – name: Elsevier Ltd |
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| SSID | ssj0005724 |
| Score | 1.8774327 |
| Snippet | This paper presents a high throughput digital design of the 128-bit Advanced Encryption Standard (AES) algorithm based on the 2-slow retiming technique on... |
| SourceID | proquest crossref elsevier |
| SourceType | Aggregation Database Enrichment Source Index Database Publisher |
| StartPage | 1014 |
| SubjectTerms | AES Algorithms Architecture C-Slow retiming Combinational logic circuits Constants Encryption Field programmable gate arrays High-throughput Optimization Pipelining Registers Transformations |
| Title | FPGA based fast and high-throughput 2-slow retiming 128-bit AES encryption algorithm |
| URI | https://dx.doi.org/10.1016/j.mejo.2014.05.004 https://www.proquest.com/docview/1567070178 |
| Volume | 45 |
| WOSCitedRecordID | wos000340219700004&url=https%3A%2F%2Fcvtisr.summon.serialssolutions.com%2F%23%21%2Fsearch%3Fho%3Df%26include.ft.matches%3Dt%26l%3Dnull%26q%3D |
| hasFullText | 1 |
| inHoldings | 1 |
| isFullTextHit | |
| isPrint | |
| journalDatabaseRights | – providerCode: PRVESC databaseName: Elsevier SD Freedom Collection Journals 2021 issn: 1879-2391 databaseCode: AIEXJ dateStart: 19950101 customDbUrl: isFulltext: true dateEnd: 99991231 titleUrlDefault: https://www.sciencedirect.com omitProxy: false ssIdentifier: ssj0005724 providerName: Elsevier |
| link | http://cvtisr.summon.serialssolutions.com/2.0.0/link/0/eLvHCXMwtV1Zj9MwELZglwd4QJza5ZKReIuC6sRukscKdTnErlZQpL5ZTpzQVm1SJeke_HpmYudQBStA4sVKrThJPZ9nxuM5CHmT6bEWCta3Bjy4XI9jN4xU7LIs8bEGHCySJmX-5-DsLJzPo3N7XFA15QSCPA-vrqLtfyU19AGxMXT2L8jdPRQ64BqIDi2QHdo_IvzJ-fuJg8JJO5mqjAM5JiV2bUme7a52PLdaF5cORjBu0FYA4gO2yLUzmX514L-U14aRqPX3olzWi81QhT1FF76-ek4fP6JKVS1UUyQYqPZDNU06gN8XLNykl-aYY1GqTWfeUdep6W-unFNVFTs9NEgw3rnDWStZGynTuyUhYw2DyPV8U5mr5bwmkaRFWDhgo1hAeCCSQQkSv2T3xvKwertJVxjIyXiThXXEe-HWuRziqTRs3iIPdpRo5RG3yaEXiAiY-eHk43T-qXcMCkwp5PaLbaiV8Qrcf9Pv1Jk9wd5oK7MH5L7dZtCJgcdDcivNH5F7g-STj8kMgUIboFAECgWg0D2gUAMU2gKFWqBQAArtgUI7oDwh306ms3cfXFtjw01836_dGK0jyMkTlsC69dhY8zTwuZfFPhcxD1PFlPYzruGXiGE3EPNA8YwJNfI9FftPyUFe5OkRoamIswjmN1I8xHEKo651ksBdTMfaOyasnSqZ2AT0WAdlLVtPw5XE6ZU4vXIkJHzWMXG6MVuTfuXGu0VLAWkVSKMYSgDMjeNet-SSwF3xyEzlabGrJBPjAOaHBeGzf3z2c3K3XyQvyEFd7tKX5E5yUS-r8pXF3k88NqAx |
| linkProvider | Elsevier |
| openUrl | ctx_ver=Z39.88-2004&ctx_enc=info%3Aofi%2Fenc%3AUTF-8&rfr_id=info%3Asid%2Fsummon.serialssolutions.com&rft_val_fmt=info%3Aofi%2Ffmt%3Akev%3Amtx%3Ajournal&rft.genre=article&rft.atitle=FPGA+based+fast+and+high-throughput+2-slow+retiming+128-bit+AES+encryption+algorithm&rft.jtitle=Microelectronics&rft.au=Farashahi%2C+Reza+Rezaeian&rft.au=Rashidi%2C+Bahram&rft.au=Sayedi%2C+Sayed+Masoud&rft.date=2014-08-01&rft.pub=Elsevier+Ltd&rft.issn=1879-2391&rft.volume=45&rft.issue=8&rft.spage=1014&rft.epage=1025&rft_id=info:doi/10.1016%2Fj.mejo.2014.05.004&rft.externalDocID=S0026269214001505 |
| thumbnail_l | http://covers-cdn.summon.serialssolutions.com/index.aspx?isbn=/lc.gif&issn=1879-2391&client=summon |
| thumbnail_m | http://covers-cdn.summon.serialssolutions.com/index.aspx?isbn=/mc.gif&issn=1879-2391&client=summon |
| thumbnail_s | http://covers-cdn.summon.serialssolutions.com/index.aspx?isbn=/sc.gif&issn=1879-2391&client=summon |