Low-Power, High-Throughput, and Low-Area Adaptive FIR Filter Based on Distributed Arithmetic

This brief presents a novel pipelined architecture for low-power, high-throughput, and low-area implementation of adaptive filter based on distributed arithmetic (DA). The throughput rate of the proposed design is significantly increased by parallel lookup table (LUT) update and concurrent implement...

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Bibliographic Details
Published in:IEEE transactions on circuits and systems. II, Express briefs Vol. 60; no. 6; pp. 346 - 350
Main Authors: Park, Sang Yoon, Meher, Pramod Kumar
Format: Journal Article
Language:English
Published: IEEE 01.06.2013
Subjects:
Adaptive filter
Adaptive filters
Arithmetic
circuit optimization
Clocks
Computer architecture
distributed arithmetic (DA)
Filtering
Finite impulse response filters
least mean square (LMS) algorithm
Multiplexing
Power demand
Table lookup
Throughput
ISSN:1549-7747, 1558-3791
Online Access:Get full text
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Summary:This brief presents a novel pipelined architecture for low-power, high-throughput, and low-area implementation of adaptive filter based on distributed arithmetic (DA). The throughput rate of the proposed design is significantly increased by parallel lookup table (LUT) update and concurrent implementation of filtering and weight-update operations. The conventional adder-based shift accumulation for DA-based inner-product computation is replaced by conditional signed carry-save accumulation in order to reduce the sampling period and area complexity. Reduction of power consumption is achieved in the proposed design by using a fast bit clock for carry-save accumulation but a much slower clock for all other operations. It involves the same number of multiplexors, smaller LUT, and nearly half the number of adders compared to the existing DA-based design. From synthesis results, it is found that the proposed design consumes 13% less power and 29% less area-delay product (ADP) over our previous DA-based adaptive filter in average for filter lengths N = 16 \ \hbox{and} \ 32 . Compared to the best of other existing designs, our proposed architecture provides 9.5 times less power and 4.6 times less ADP.
ISSN:1549-7747
1558-3791
DOI:10.1109/TCSII.2013.2251968