Towards a performance-portable description of geometric multigrid algorithms using a domain-specific language

High Performance Computing (HPC) systems are nowadays more and more heterogeneous. Different processor types can be found on a single node including accelerators such as Graphics Processing Units (GPUs). To cope with the challenge of programming such complex systems, this work presents a domain-spec...

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Published in:	Journal of parallel and distributed computing Vol. 74; no. 12; pp. 3191 - 3201
Main Authors:	Membarth, Richard, Reiche, Oliver, Schmitt, Christian, Hannig, Frank, Teich, Jürgen, Stürmer, Markus, Köstler, Harald
Format:	Journal Article
Language:	English
Published:	Elsevier Inc 01.12.2014
Subjects:	Accelerators Algorithms Code generation CUDA Distributed processing Domain-specific language GPU Graphics processing units Image processing Image pyramid Mathematical models Microprocessors Multigrid Multiresolution OpenCL Stencil codes Subscriber line Code generation CUDA Domain-specific language Multigrid Multiresolution Image pyramid Stencil codes OpenCL GPU
ISSN:	0743-7315, 1096-0848
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Abstract	High Performance Computing (HPC) systems are nowadays more and more heterogeneous. Different processor types can be found on a single node including accelerators such as Graphics Processing Units (GPUs). To cope with the challenge of programming such complex systems, this work presents a domain-specific approach to automatically generate code tailored to different processor types. Low-level CUDA and OpenCL code is generated from a high-level description of an algorithm specified in a Domain-Specific Language (DSL) instead of writing hand-tuned code for GPU accelerators. The DSL is part of the Heterogeneous Image Processing Acceleration (HIPAcc) framework and was extended in this work to handle grid hierarchies in order to model different cycle types. Language constructs are introduced to process and represent data at different resolutions. This allows to describe image processing algorithms that work on image pyramids as well as multigrid methods in the stencil domain. By decoupling the algorithm from its schedule, the proposed approach allows to generate efficient stencil code implementations. Our results show that similar performance compared to hand-tuned codes can be achieved. •DSL extension to handle image pyramids and grid hierarchies.•DSL extension to model different multigrid cycle types.•Generated GPU code shows similar performance compared to hand-tuned implementation.•We apply the algorithm to high dynamic range compression of 2D X-ray images.
AbstractList	High Performance Computing (HPC) systems are nowadays more and more heterogeneous. Different processor types can be found on a single node including accelerators such as Graphics Processing Units (GPUs). To cope with the challenge of programming such complex systems, this work presents a domain-specific approach to automatically generate code tailored to different processor types. Low-level CUDA and OpenCL code is generated from a high-level description of an algorithm specified in a Domain-Specific Language (DSL) instead of writing hand-tuned code for GPU accelerators. The DSL is part of the Heterogeneous Image Processing Acceleration (HIPA cc ) framework and was extended in this work to handle grid hierarchies in order to model different cycle types. Language constructs are introduced to process and represent data at different resolutions. This allows to describe image processing algorithms that work on image pyramids as well as multigrid methods in the stencil domain. By decoupling the algorithm from its schedule, the proposed approach allows to generate efficient stencil code implementations. Our results show that similar performance compared to hand-tuned codes can be achieved. High Performance Computing (HPC) systems are nowadays more and more heterogeneous. Different processor types can be found on a single node including accelerators such as Graphics Processing Units (GPUs). To cope with the challenge of programming such complex systems, this work presents a domain-specific approach to automatically generate code tailored to different processor types. Low-level CUDA and OpenCL code is generated from a high-level description of an algorithm specified in a Domain-Specific Language (DSL) instead of writing hand-tuned code for GPU accelerators. The DSL is part of the Heterogeneous Image Processing Acceleration (HIPAcc) framework and was extended in this work to handle grid hierarchies in order to model different cycle types. Language constructs are introduced to process and represent data at different resolutions. This allows to describe image processing algorithms that work on image pyramids as well as multigrid methods in the stencil domain. By decoupling the algorithm from its schedule, the proposed approach allows to generate efficient stencil code implementations. Our results show that similar performance compared to hand-tuned codes can be achieved. •DSL extension to handle image pyramids and grid hierarchies.•DSL extension to model different multigrid cycle types.•Generated GPU code shows similar performance compared to hand-tuned implementation.•We apply the algorithm to high dynamic range compression of 2D X-ray images.
Author	Hannig, Frank Köstler, Harald Reiche, Oliver Membarth, Richard Teich, Jürgen Stürmer, Markus Schmitt, Christian
Author_xml	– sequence: 1 givenname: Richard surname: Membarth fullname: Membarth, Richard email: richard.membarth@dfki.de organization: German Research Center for Artificial Intelligence, Germany – sequence: 2 givenname: Oliver surname: Reiche fullname: Reiche, Oliver email: oliver.reiche@cs.fau.de organization: Hardware/Software Co-Design, Department of Computer Science, University of Erlangen-Nuremberg, Germany – sequence: 3 givenname: Christian surname: Schmitt fullname: Schmitt, Christian email: christian.schmitt@cs.fau.de organization: Hardware/Software Co-Design, Department of Computer Science, University of Erlangen-Nuremberg, Germany – sequence: 4 givenname: Frank surname: Hannig fullname: Hannig, Frank email: hannig@cs.fau.de organization: Hardware/Software Co-Design, Department of Computer Science, University of Erlangen-Nuremberg, Germany – sequence: 5 givenname: Jürgen surname: Teich fullname: Teich, Jürgen email: teich@cs.fau.de organization: Hardware/Software Co-Design, Department of Computer Science, University of Erlangen-Nuremberg, Germany – sequence: 6 givenname: Markus surname: Stürmer fullname: Stürmer, Markus email: markus.stuermer@cs.fau.de organization: System Simulation, Department of Computer Science, University of Erlangen-Nuremberg, Germany – sequence: 7 givenname: Harald surname: Köstler fullname: Köstler, Harald email: harald.koestler@cs.fau.de organization: System Simulation, Department of Computer Science, University of Erlangen-Nuremberg, Germany
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Snippet	High Performance Computing (HPC) systems are nowadays more and more heterogeneous. Different processor types can be found on a single node including...
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SubjectTerms	Accelerators Algorithms Code generation CUDA Distributed processing Domain-specific language GPU Graphics processing units Image processing Image pyramid Mathematical models Microprocessors Multigrid Multiresolution OpenCL Stencil codes Subscriber line
Title	Towards a performance-portable description of geometric multigrid algorithms using a domain-specific language
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