The SegBus platform – architecture and communication mechanisms

In this study, we introduce the SegBus architecture, a synchronous segmented bus platform for systems on chip. We present the envisioned structure in detail, and also address aspects of communication on the platform. The motivation behind SegBus is the search for performance improvements, in several...

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Veröffentlicht in:Journal of systems architecture Jg. 53; H. 4; S. 151 - 169
1. Verfasser: Seceleanu, Tiberiu
Format: Journal Article
Sprache:Englisch
Veröffentlicht: Amsterdam Elsevier B.V 01.04.2007
Elsevier Sequoia S.A
Schlagworte:
Computer architecture
Computer platforms
Field programmable gate arrays
FPGA
On-chip communication
Platform design
Segmented bus
Studies
Platform design
Segmented bus
On-chip communication
FPGA
ISSN:1383-7621, 1873-6165
Online-Zugang:Volltext
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Beschreibung
Zusammenfassung:In this study, we introduce the SegBus architecture, a synchronous segmented bus platform for systems on chip. We present the envisioned structure in detail, and also address aspects of communication on the platform. The motivation behind SegBus is the search for performance improvements, in several directions, such as global throughput, power consumption, modularity, adaptability. By means of an example, we illustrate the capabilities of the described architecture. The implementation strategy targets FPGA technology, and allows for the utilization of multiple clock domains. The platform emerges as a highly design-time configurable system, adaptable to various design constraints.
Bibliographie:SourceType-Scholarly Journals-1
ObjectType-Feature-1
content type line 14
ISSN:1383-7621
1873-6165
DOI:10.1016/j.sysarc.2006.07.002