Adaptive fault-tolerant architecture and routing algorithm for reliable many-core 3D-NoC systems

During the last few decades, Three-dimensional Network-on-Chips (3D-NoCs) have been showing their advantages against 2D-NoC architectures. This is thanks to the reduced average interconnect length and lower interconnect-power consumption inherited from Three-dimensional Integrated Circuits (3D-ICs)....

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Bibliographic Details
Published in:Journal of parallel and distributed computing Vol. 93-94; pp. 30 - 43
Main Authors: Ben Ahmed, Akram, Ben Abdallah, Abderazek
Format: Journal Article
Language:English
Published: Elsevier Inc 01.07.2016
Subjects:
3D NoC
Algorithms
Architecture
Computer networks
Deadlock-free
Dynamic reconfiguration
Fault tolerance
Faults
Performance degradation
Robustness
Routing (telecommunications)
Three dimensional
Robustness
Fault-tolerance
Architecture
Deadlock-free
3D NoC
Dynamic reconfiguration
ISSN:0743-7315, 1096-0848
Online Access:Get full text
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Summary:During the last few decades, Three-dimensional Network-on-Chips (3D-NoCs) have been showing their advantages against 2D-NoC architectures. This is thanks to the reduced average interconnect length and lower interconnect-power consumption inherited from Three-dimensional Integrated Circuits (3D-ICs). On the other hand, questions about their reliability is starting to arise. This issue is mainly caused by their complex nature where a single faulty transistor may cause intolerable performance degradation or even the entire system collapse. To ensure their correct functionality, 3D-NoC systems must be fault-tolerant to any short-term malfunction or permanent physical damage to ensure message delivery on time while minimizing the performance degradation as much as possible. In this paper, we present a fault-tolerant 3D-NoC architecture, called 3D-Fault-Tolerant-OASIS (3D-FTO).11This project is partially supported by Competitive research funding, Ref. P1-5, Fukushima, Japan. With the aid of a light-weight routing algorithm, 3D-FTO manages to avoid the system failure at the presence of a large number of transient, intermittent, and permanent faults. Moreover, the proposed architecture is leveraging on reconfigurable components to handle the fault occurrence in links, input-buffers, and crossbar, where the faults are more often to happen. The proposed 3D-FTO system is able to work around different kinds of faults ensuring graceful performance degradation while minimizing the additional hardware complexity and remaining power-efficient. •Adaptive fault-tolerant 3D-Network-on-Chip system architecture.•RAB mechanism for deadlock recovery and fault-tolerance in input-buffers.•Traffic-Prediction-Unit technique for congestion relief.•Bypass-Link-on-Demand to tackle fault-occurrence in the Crossbar.•Fault-tolerance and graceful performance degradation obtained at high fault-rates.
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ISSN:0743-7315
1096-0848
DOI:10.1016/j.jpdc.2016.03.014