Liu, L., Jin, Y., Liu, Y., Ma, N., Huan, Y., Zou, Z., & Zheng, L. (2018). A Design of Autonomous Error-Tolerant Architectures for Massively Parallel Computing. IEEE transactions on very large scale integration (VLSI) systems, 26(10), 2143-2154. https://doi.org/10.1109/TVLSI.2018.2846298
Chicago-Zitierstil (17. Ausg.)Liu, Lizheng, Yi Jin, Yi Liu, Ning Ma, Yuxiang Huan, Zhuo Zou, und Lirong Zheng. "A Design of Autonomous Error-Tolerant Architectures for Massively Parallel Computing." IEEE Transactions on Very Large Scale Integration (VLSI) Systems 26, no. 10 (2018): 2143-2154. https://doi.org/10.1109/TVLSI.2018.2846298.
MLA-Zitierstil (9. Ausg.)Liu, Lizheng, et al. "A Design of Autonomous Error-Tolerant Architectures for Massively Parallel Computing." IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol. 26, no. 10, 2018, pp. 2143-2154, https://doi.org/10.1109/TVLSI.2018.2846298.