RoB-Router : A Reorder Buffer Enabled Low Latency Network-on-Chip Router

Traditional input-queued routers in network-on-chips (NoCs) only have a small number of virtual channels (VCs) and packets in a VC are organized in a fixed order. Such design is susceptible to head-of-line (HoL) blocking as only the packet at the head of a VC can be allocated by the switch allocator...

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Veröffentlicht in:	IEEE transactions on parallel and distributed systems Jg. 29; H. 9; S. 2090 - 2104
Hauptverfasser:	Li, Cunlu, Dong, Dezun, Lu, Zhonghai, Liao, Xiangke
Format:	Journal Article
Sprache:	Englisch
Veröffentlicht:	New York IEEE 01.09.2018 The Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Schlagworte:	Buffers Communications traffic Complexity theory Network latency Network on chip Packet switching packets scheduling Performance degradation Performance enhancement Pipelines Queues reorder buffer Resource management Routers Scheduling switch allocation Switches System on chip
ISSN:	1045-9219, 1558-2183, 1558-2183
Online-Zugang:	Volltext
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