HEPCloud: An FPGA-Based Multicore Processor for FV Somewhat Homomorphic Function Evaluation

In this paper, we present an FPGA based hardware accelerator '<inline-formula><tex-math notation="LaTeX"> \mathsf{HEPCloud}</tex-math> <inline-graphic xlink:href="sinharoy-ieq1-2816640.gif"/> </inline-formula>' for homomorphic evaluations o...

Ausführliche Beschreibung

Gespeichert in:

Bibliographische Detailangaben
Veröffentlicht in:	IEEE transactions on computers Jg. 67; H. 11; S. 1637 - 1650
Hauptverfasser:	Sinha Roy, Sujoy, Jarvinen, Kimmo, Vliegen, Jo, Vercauteren, Frederik, Verbauwhede, Ingrid
Format:	Journal Article
Sprache:	Englisch
Veröffentlicht:	New York IEEE 01.11.2018 The Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Schlagworte:	Acceleration Algorithms Cloud computing Computer architecture Computer memory Cybersecurity Encryption Feasibility studies Field programmable gate arrays Hardware hardware implementation Homomorphic encryption lattice-based cryptography Microprocessors number theoretic transform Parallel processing Parameters Pipelining (computers) polynomial multiplication Polynomials ring-LWE Rings (mathematics)
ISSN:	0018-9340, 1557-9956
Online-Zugang:	Volltext
Tags:	Tag hinzufügen Keine Tags, Fügen Sie den ersten Tag hinzu!

Abstract	In this paper, we present an FPGA based hardware accelerator '<inline-formula><tex-math notation="LaTeX"> \mathsf{HEPCloud}</tex-math> <inline-graphic xlink:href="sinharoy-ieq1-2816640.gif"/> </inline-formula>' for homomorphic evaluations of medium depth functions which has applications in cloud computing. Our <inline-formula><tex-math notation="LaTeX">\mathsf{HEPCloud}</tex-math> <inline-graphic xlink:href="sinharoy-ieq2-2816640.gif"/> </inline-formula> architecture supports the polynomial ring based homomorphic encryption scheme FV for a ring-LWE parameter set of dimension <inline-formula> <tex-math notation="LaTeX">2^{15}</tex-math> <inline-graphic xlink:href="sinharoy-ieq3-2816640.gif"/> </inline-formula>, modulus size 1,228-bit, and a standard deviation 50. This parameter-set offers a multiplicative depth 36 and at least 85 bit security. The processor of <inline-formula><tex-math notation="LaTeX"> \mathsf{HEPCloud}</tex-math> <inline-graphic xlink:href="sinharoy-ieq4-2816640.gif"/> </inline-formula> is composed of multiple parallel cores. To achieve fast computation time for such a large parameter-set, various optimizations in both algorithm and architecture levels are performed. For fast polynomial multiplications, we use CRT with NTT and achieve two dimensional parallelism in <inline-formula> <tex-math notation="LaTeX">\mathsf{HEPCloud}</tex-math> <inline-graphic xlink:href="sinharoy-ieq5-2816640.gif"/> </inline-formula>. We optimize the BRAM access, use a fast Barrett like polynomial reduction method, optimize the cost of CRT, and design a fast divide-and-round unit. Beside parallel processing, we apply pipelining strategy in several of the sequential building blocks to reduce the impact of sequential computations. Finally, we implement <inline-formula><tex-math notation="LaTeX"> \mathsf{HEPCloud}</tex-math> <inline-graphic xlink:href="sinharoy-ieq6-2816640.gif"/> </inline-formula> on a medium-size Xilinx Virtex 6 FPGA board ML605 board and measure its on-board performance. To store the ciphertexts during a homomorphic function evaluation, we use the large DDR3 memory of the ML605 board. Our FPGA-based implementation of <inline-formula><tex-math notation="LaTeX">\mathsf{HEPCloud}</tex-math> <inline-graphic xlink:href="sinharoy-ieq7-2816640.gif"/> </inline-formula> computes a homomorphic multiplication in 26.67 s, of which the actual computation takes only 3.36 s and the rest is spent for off-chip memory access. It requires about 37,551 s to evaluate the SIMON-64/128 block cipher, but the per-block timing is only about 18 s because <inline-formula><tex-math notation="LaTeX">\mathsf{HEPCloud}</tex-math> <inline-graphic xlink:href="sinharoy-ieq8-2816640.gif"/> </inline-formula> processes 2,048 blocks simultaneously. The results show that FPGA-based acceleration of homomorphic function evaluations is feasible, but fast memory interface is crucial for the performance.
AbstractList	In this paper, we present an FPGA based hardware accelerator '<inline-formula><tex-math notation="LaTeX"> \mathsf{HEPCloud}</tex-math> <inline-graphic xlink:href="sinharoy-ieq1-2816640.gif"/> </inline-formula>' for homomorphic evaluations of medium depth functions which has applications in cloud computing. Our <inline-formula><tex-math notation="LaTeX">\mathsf{HEPCloud}</tex-math> <inline-graphic xlink:href="sinharoy-ieq2-2816640.gif"/> </inline-formula> architecture supports the polynomial ring based homomorphic encryption scheme FV for a ring-LWE parameter set of dimension <inline-formula> <tex-math notation="LaTeX">2^{15}</tex-math> <inline-graphic xlink:href="sinharoy-ieq3-2816640.gif"/> </inline-formula>, modulus size 1,228-bit, and a standard deviation 50. This parameter-set offers a multiplicative depth 36 and at least 85 bit security. The processor of <inline-formula><tex-math notation="LaTeX"> \mathsf{HEPCloud}</tex-math> <inline-graphic xlink:href="sinharoy-ieq4-2816640.gif"/> </inline-formula> is composed of multiple parallel cores. To achieve fast computation time for such a large parameter-set, various optimizations in both algorithm and architecture levels are performed. For fast polynomial multiplications, we use CRT with NTT and achieve two dimensional parallelism in <inline-formula> <tex-math notation="LaTeX">\mathsf{HEPCloud}</tex-math> <inline-graphic xlink:href="sinharoy-ieq5-2816640.gif"/> </inline-formula>. We optimize the BRAM access, use a fast Barrett like polynomial reduction method, optimize the cost of CRT, and design a fast divide-and-round unit. Beside parallel processing, we apply pipelining strategy in several of the sequential building blocks to reduce the impact of sequential computations. Finally, we implement <inline-formula><tex-math notation="LaTeX"> \mathsf{HEPCloud}</tex-math> <inline-graphic xlink:href="sinharoy-ieq6-2816640.gif"/> </inline-formula> on a medium-size Xilinx Virtex 6 FPGA board ML605 board and measure its on-board performance. To store the ciphertexts during a homomorphic function evaluation, we use the large DDR3 memory of the ML605 board. Our FPGA-based implementation of <inline-formula><tex-math notation="LaTeX">\mathsf{HEPCloud}</tex-math> <inline-graphic xlink:href="sinharoy-ieq7-2816640.gif"/> </inline-formula> computes a homomorphic multiplication in 26.67 s, of which the actual computation takes only 3.36 s and the rest is spent for off-chip memory access. It requires about 37,551 s to evaluate the SIMON-64/128 block cipher, but the per-block timing is only about 18 s because <inline-formula><tex-math notation="LaTeX">\mathsf{HEPCloud}</tex-math> <inline-graphic xlink:href="sinharoy-ieq8-2816640.gif"/> </inline-formula> processes 2,048 blocks simultaneously. The results show that FPGA-based acceleration of homomorphic function evaluations is feasible, but fast memory interface is crucial for the performance. In this paper, we present an FPGA based hardware accelerator ‘[Formula Omitted]’ for homomorphic evaluations of medium depth functions which has applications in cloud computing. Our [Formula Omitted] architecture supports the polynomial ring based homomorphic encryption scheme FV for a ring-LWE parameter set of dimension [Formula Omitted], modulus size 1,228-bit, and a standard deviation 50. This parameter-set offers a multiplicative depth 36 and at least 85 bit security. The processor of [Formula Omitted] is composed of multiple parallel cores. To achieve fast computation time for such a large parameter-set, various optimizations in both algorithm and architecture levels are performed. For fast polynomial multiplications, we use CRT with NTT and achieve two dimensional parallelism in [Formula Omitted]. We optimize the BRAM access, use a fast Barrett like polynomial reduction method, optimize the cost of CRT, and design a fast divide-and-round unit. Beside parallel processing, we apply pipelining strategy in several of the sequential building blocks to reduce the impact of sequential computations. Finally, we implement [Formula Omitted] on a medium-size Xilinx Virtex 6 FPGA board ML605 board and measure its on-board performance. To store the ciphertexts during a homomorphic function evaluation, we use the large DDR3 memory of the ML605 board. Our FPGA-based implementation of [Formula Omitted] computes a homomorphic multiplication in 26.67 s, of which the actual computation takes only 3.36 s and the rest is spent for off-chip memory access. It requires about 37,551 s to evaluate the SIMON-64/128 block cipher, but the per-block timing is only about 18 s because [Formula Omitted] processes 2,048 blocks simultaneously. The results show that FPGA-based acceleration of homomorphic function evaluations is feasible, but fast memory interface is crucial for the performance.
Author	Verbauwhede, Ingrid Jarvinen, Kimmo Vliegen, Jo Vercauteren, Frederik Sinha Roy, Sujoy
Author_xml	– sequence: 1 givenname: Sujoy orcidid: 0000-0002-9805-5389 surname: Sinha Roy fullname: Sinha Roy, Sujoy email: sujoy.sinharoy@esat.kuleuven.be organization: KU Leuven ESAT/COSIC and IMEC, Kasteelpark Arenberg 10, Leuven-Heverlee, Belgium – sequence: 2 givenname: Kimmo orcidid: 0000-0001-8012-2881 surname: Jarvinen fullname: Jarvinen, Kimmo email: kimmo.u.jarvinen@helsinki.fi organization: Department of Computer Science, University of Helsinki, Gustaf Hällströmin katu 2b, Helsinki, Finland – sequence: 3 givenname: Jo surname: Vliegen fullname: Vliegen, Jo email: jo.vliegen@esat.kuleuven.be organization: KU Leuven ESAT/COSIC and IMEC, Kasteelpark Arenberg 10, Leuven-Heverlee, Belgium – sequence: 4 givenname: Frederik orcidid: 0000-0002-7208-9599 surname: Vercauteren fullname: Vercauteren, Frederik email: frederik.vercauteren@esat.kuleuven.be organization: KU Leuven ESAT/COSIC and IMEC, Kasteelpark Arenberg 10, Leuven-Heverlee, Belgium – sequence: 5 givenname: Ingrid orcidid: 0000-0002-0879-076X surname: Verbauwhede fullname: Verbauwhede, Ingrid email: Ingrid.Verbauwhede@esat.kuleuven.be organization: KU Leuven ESAT/COSIC and IMEC, Kasteelpark Arenberg 10, Leuven-Heverlee, Belgium
BookMark	eNp9UEFLwzAUDjLBbXr24CXgudtLs6aNt1nWTZg4cHrxENI0ZR1dM5NW8d-bueHBgzw-3oP3fd97fAPUa0yjEbomMCIE-HidjkIgyShMCGMTOEN9EkVxwHnEeqgPfhVwOoELNHBuCwAsBN5Hb4vZKq1NV9zhaYOz1Xwa3EunC_zY1W2ljNV4ZY3SzhmLS4_sFT-bnf7cyBYvzM6X3W8qhbOuUW1lGjz7kHUnD-MlOi9l7fTVqQ_RSzZbp4tg-TR_SKfLQFEKbVBCTCWEVHJO2ETGush5HmsKMvcEnTBQOSOKx2UeK19FXlAmIYpCpSfegQ7R7dF3b817p10rtqazjT8pQkJikoQenhUdWcoa56wuharanz9bK6taEBCHHMU6FYccxSlHrxv_0e1ttZP26x_FzVFRaa1_2QklCUsI_QYzt34y
CODEN	ITCOB4
CitedBy_id	crossref_primary_10_1109_TPDS_2020_3021238 crossref_primary_10_1109_TVLSI_2023_3288754 crossref_primary_10_1109_TCSI_2022_3166550 crossref_primary_10_1007_s11227_021_03980_5 crossref_primary_10_1109_TVLSI_2020_3010585 crossref_primary_10_1109_TCSII_2023_3295614 crossref_primary_10_1109_TPDS_2022_3228628 crossref_primary_10_1109_TCSII_2023_3344604 crossref_primary_10_1109_TVLSI_2022_3166355 crossref_primary_10_1109_ACCESS_2020_3023255 crossref_primary_10_1109_TCAD_2024_3496836 crossref_primary_10_1109_TVLSI_2023_3277865 crossref_primary_10_1109_TC_2020_3017930 crossref_primary_10_1109_ACCESS_2021_3096189 crossref_primary_10_1109_TVLSI_2023_3303352 crossref_primary_10_1109_TVLSI_2019_2943127 crossref_primary_10_1109_TCAD_2023_3292211 crossref_primary_10_1109_TIFS_2023_3338553 crossref_primary_10_1109_TC_2022_3198628 crossref_primary_10_1109_TCSII_2023_3289489 crossref_primary_10_1109_ACCESS_2022_3143804 crossref_primary_10_1109_TETC_2019_2902799 crossref_primary_10_1007_s13389_025_00376_6 crossref_primary_10_1109_ACCESS_2024_3473901 crossref_primary_10_1109_TC_2020_2988765 crossref_primary_10_1109_ACCESS_2024_3473903 crossref_primary_10_1109_ACCESS_2024_3354275 crossref_primary_10_1109_ACCESS_2024_3386977 crossref_primary_10_1109_TC_2024_3449121 crossref_primary_10_1109_TCSI_2022_3163970
Cites_doi	10.1007/s10623-012-9720-4 10.1007/978-3-642-45239-0_4 10.1145/2046660.2046682 10.1007/978-3-662-44709-3_20 10.1147/sj.294.0526 10.1109/TETC.2016.2619669 10.1145/1536414.1536440 10.1109/ISCAS.2013.6572408 10.1109/TC.2015.2498606 10.1007/978-3-319-70278-0_6 10.1109/TVLSI.2013.2281786 10.1109/TC.2016.2574340 10.1007/978-3-662-53018-4_6 10.1007/978-3-642-41320-9_16 10.1145/279232.279237
ContentType	Journal Article
Copyright	Copyright The Institute of Electrical and Electronics Engineers, Inc. (IEEE) 2018
Copyright_xml	– notice: Copyright The Institute of Electrical and Electronics Engineers, Inc. (IEEE) 2018
DBID	97E RIA RIE AAYXX CITATION 7SC 7SP 8FD JQ2 L7M L~C L~D
DOI	10.1109/TC.2018.2816640
DatabaseName	IEEE Xplore (IEEE) IEEE All-Society Periodicals Package (ASPP) 1998–Present IEEE Electronic Library (IEL) CrossRef Computer and Information Systems Abstracts Electronics & Communications Abstracts Technology Research Database ProQuest Computer Science Collection Advanced Technologies Database with Aerospace Computer and Information Systems Abstracts Academic Computer and Information Systems Abstracts Professional
DatabaseTitle	CrossRef Technology Research Database Computer and Information Systems Abstracts – Academic Electronics & Communications Abstracts ProQuest Computer Science Collection Computer and Information Systems Abstracts Advanced Technologies Database with Aerospace Computer and Information Systems Abstracts Professional
DatabaseTitleList	Technology Research Database
Database_xml	– sequence: 1 dbid: RIE name: IEEE Electronic Library (IEL) url: https://ieeexplore.ieee.org/ sourceTypes: Publisher
DeliveryMethod	fulltext_linktorsrc
Discipline	Engineering Computer Science
EISSN	1557-9956
EndPage	1650
ExternalDocumentID	10_1109_TC_2018_2816640 8318681
Genre	orig-research
GrantInformation_xml	– fundername: Hercules Foundation grantid: AKUL/11/19 – fundername: WITDOM grantid: H2020-ICT-2014-644209 HEAT; H2020-ICT-2014-645622 PQCRYPTO – fundername: ICT Programme – fundername: Flemish Government – fundername: Horizon 2020 Research and Innovation Programme grantid: H2020-ICT-2014-644371 – fundername: Cathedral ERC Advanced grantid: 695305 – fundername: Research Council KU Leuven grantid: C16/15/058 – fundername: Academy of Finland grantid: 283250; 303578 – fundername: European Commission
GroupedDBID	--Z -DZ -~X .DC 0R~ 29I 4.4 5GY 6IK 85S 97E AAJGR AARMG AASAJ AAWTH ABAZT ABQJQ ABVLG ACGFO ACIWK ACNCT AENEX AETEA AGQYO AHBIQ AKJIK AKQYR ALMA_UNASSIGNED_HOLDINGS ASUFR ATWAV BEFXN BFFAM BGNUA BKEBE BPEOZ CS3 DU5 EBS EJD HZ~ IEDLZ IFIPE IPLJI JAVBF LAI M43 MS~ O9- OCL P2P PQQKQ RIA RIE RNS RXW TAE TN5 TWZ UHB UPT XZL YZZ .55 3EH 3O- 5VS AAYXX ABFSI ABUFD AETIX AGSQL AI. AIBXA ALLEH CITATION E.L H~9 IAAWW IBMZZ ICLAB IFJZH MVM RNI RZB UKR VH1 X7M XOL YXB YYQ ZCG 7SC 7SP 8FD JQ2 L7M L~C L~D
ID	FETCH-LOGICAL-c330t-f073a023a99164a7edb9b7e30abc33e860cb61c97fb7c7c7dbd36a0552ce43303
IEDL.DBID	RIE
ISICitedReferencesCount	52
ISICitedReferencesURI	http://www.webofscience.com/api/gateway?GWVersion=2&SrcApp=Summon&SrcAuth=ProQuest&DestLinkType=CitingArticles&DestApp=WOS_CPL&KeyUT=000446704900010&url=https%3A%2F%2Fcvtisr.summon.serialssolutions.com%2F%23%21%2Fsearch%3Fho%3Df%26include.ft.matches%3Dt%26l%3Dnull%26q%3D
ISSN	0018-9340
IngestDate	Mon Jun 30 05:45:49 EDT 2025 Sat Nov 29 01:35:40 EST 2025 Tue Nov 18 22:31:17 EST 2025 Wed Aug 27 02:52:25 EDT 2025
IsDoiOpenAccess	false
IsOpenAccess	true
IsPeerReviewed	true
IsScholarly	true
Issue	11
Language	English
License	https://ieeexplore.ieee.org/Xplorehelp/downloads/license-information/IEEE.html
LinkModel	DirectLink
MergedId	FETCHMERGED-LOGICAL-c330t-f073a023a99164a7edb9b7e30abc33e860cb61c97fb7c7c7dbd36a0552ce43303
Notes	ObjectType-Article-1 SourceType-Scholarly Journals-1 ObjectType-Feature-2 content type line 14
ORCID	0000-0001-8012-2881 0000-0002-7208-9599 0000-0002-0879-076X 0000-0002-9805-5389
OpenAccessLink	http://hdl.handle.net/10138/308151
PQID	2117182718
PQPubID	85452
PageCount	14
ParticipantIDs	proquest_journals_2117182718 ieee_primary_8318681 crossref_citationtrail_10_1109_TC_2018_2816640 crossref_primary_10_1109_TC_2018_2816640
PublicationCentury	2000
PublicationDate	2018-11-01
PublicationDateYYYYMMDD	2018-11-01
PublicationDate_xml	– month: 11 year: 2018 text: 2018-11-01 day: 01
PublicationDecade	2010
PublicationPlace	New York
PublicationPlace_xml	– name: New York
PublicationTitle	IEEE transactions on computers
PublicationTitleAbbrev	TC
PublicationYear	2018
Publisher	IEEE The Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher_xml	– name: IEEE – name: The Institute of Electrical and Electronics Engineers, Inc. (IEEE)
References	ref13 lyubashevsky (ref24) 2010 ref36 ref10 cormen (ref11) 2001 brakerski (ref7) 2012 ref17 pöppelmann (ref29) 2014 cathébras (ref9) 2017 coron (ref12) 2014 hankerson (ref20) 2003 pöppelmann (ref30) 2014 (ref21) 2017 vercauteren (ref38) 2014 doröz (ref15) 2013 pöppelmann (ref31) 2015 bos (ref5) 2017 lepoint (ref23) 2014 rivest (ref32) 1978; 4 von zur gathen (ref39) 1999 smart (ref35) 2010 sinha roy (ref34) 2014 ref26 ref41 barrett (ref2) 1987 ref22 gentry (ref18) 2012 albrecht (ref1) 2017 albrecht (ref25) 2016 ref28 ref27 beaulieu (ref3) 2013 ref8 fan (ref16) 2012 sinha roy (ref33) 2015 doröz (ref14) 2015 boneh (ref4) 1999; 46 ref6 ref40 van dijk (ref37) 2010 gentry (ref19) 2013
References_xml	– start-page: 75 year: 2013 ident: ref19 article-title: Homomorphic encryption from learning with errors: Conceptually-simpler, asymptotically-faster, attribute-based publication-title: Proceedings of the Advances in Cryptology-CRYPTO – year: 2001 ident: ref11 publication-title: Introduction to Algorithms – ident: ref36 doi: 10.1007/s10623-012-9720-4 – year: 2012 ident: ref16 article-title: Somewhat practical fully homomorphic encryption – start-page: 371 year: 2014 ident: ref34 article-title: Compact ring-LWE cryptoprocessor publication-title: Proc Int Workshop Cryptographic Hardware Embedded Syst – volume: 46 start-page: 203 year: 1999 ident: ref4 article-title: Twenty years of attacks on the RSA cryptosystem publication-title: Notices Amer Math Soc – start-page: 850 year: 2012 ident: ref18 article-title: Homomorphic evaluation of the AES circuit publication-title: Proc 32nd Annu Cryptology Conf Adv Cryptology – ident: ref6 doi: 10.1007/978-3-642-45239-0_4 – start-page: 318 year: 2014 ident: ref23 article-title: A comparison of the homomorphic encryption schemes FV and YASHE publication-title: Proc Int Conf Cryptology Africa – start-page: 164 year: 2015 ident: ref33 article-title: Modular hardware architecture for somewhat homomorphic function evaluation publication-title: Proc Int Workshop Cryptogr Hardware Embedded Syst – ident: ref27 doi: 10.1145/2046660.2046682 – year: 2014 ident: ref29 article-title: Enhanced lattice-based signatures on reconfigurable hardware doi: 10.1007/978-3-662-44709-3_20 – year: 1999 ident: ref39 publication-title: Modern Computer Algebra – ident: ref10 doi: 10.1147/sj.294.0526 – ident: ref13 doi: 10.1109/TETC.2016.2619669 – year: 2013 ident: ref3 article-title: The SIMON and SPECK families of lightweight block ciphers – ident: ref17 doi: 10.1145/1536414.1536440 – start-page: 1 year: 2010 ident: ref24 article-title: On ideal lattices and learning with errors over rings publication-title: Proc Int Conf Theory Appl Cryptographic Techn – ident: ref40 doi: 10.1109/ISCAS.2013.6572408 – start-page: 185 year: 2015 ident: ref14 article-title: Accelerating LTV based homomorphic encryption in reconfigurable hardware publication-title: Proc Int Workshop Cryptogr Hardware Embedded Syst – ident: ref8 doi: 10.1109/TC.2015.2498606 – start-page: 868 year: 2012 ident: ref7 article-title: Fully homomorphic encryption without modulus switching from classical GapSVP publication-title: Proc 32nd Annu Cryptology Conf Adv Cryptology – year: 2017 ident: ref9 article-title: An analysis of FV parameters impact towards its hardware acceleration doi: 10.1007/978-3-319-70278-0_6 – ident: ref41 doi: 10.1109/TVLSI.2013.2281786 – start-page: 420 year: 2010 ident: ref35 article-title: Fully homomorphic encryption with relatively small key and ciphertext sizes publication-title: Proc 13th Int Conf Practice Theory Public Key Cryptography – year: 2003 ident: ref20 publication-title: Guide to Elliptic Curve Cryptography – start-page: 68 year: 2014 ident: ref30 article-title: Towards practical lattice-based public-key encryption on reconfigurable hardware publication-title: Proc Conf Sel Areas Cryptography – start-page: 24 year: 2010 ident: ref37 article-title: Fully homomorphic encryption over the integers publication-title: Proc Int Conf Theory Appl Cryptographic Techn – start-page: 311 year: 2014 ident: ref12 article-title: Scale-invariant fully homomorphic encryption over the integers publication-title: Proc Int Workshop Public Key Cryptogr – ident: ref28 doi: 10.1109/TC.2016.2574340 – start-page: 143 year: 2015 ident: ref31 article-title: Accelerating homomorphic evaluation on reconfigurable hardware publication-title: Proc Int Workshop Cryptogr Hardware Embedded Syst – start-page: 955 year: 2013 ident: ref15 article-title: Evaluating the hardware performance of a million-bit multiplier publication-title: Proc 16th Euromicro Conf Digit Sys Des – start-page: 187 year: 2017 ident: ref5 article-title: Privacy-friendly forecasting for the smart grid using homomorphic encryption and the group method of data handling publication-title: Proc Int Conf Cryptology Africa – year: 2016 ident: ref25 article-title: A subfield lattice attack on overstretched NTRU assumptions: Cryptanalysis of some FHE and graded encoding schemes doi: 10.1007/978-3-662-53018-4_6 – ident: ref26 doi: 10.1007/978-3-642-41320-9_16 – year: 2017 ident: ref21 article-title: Core i7-2600 processor. – start-page: 311 year: 1987 ident: ref2 article-title: Implementing the Rivest Shamir and Adleman public key encryption algorithm on a standard digital signal processor publication-title: Proc Int Conf Theory Appl Cryptographic Techn – year: 2017 ident: ref1 article-title: Complexity estimates for solving LWE. – volume: 4 start-page: 169 year: 1978 ident: ref32 article-title: On data banks and privacy homomorphisms publication-title: Found Secure Comput – year: 2014 ident: ref38 article-title: Fully homomorphic encryption. – ident: ref22 doi: 10.1145/279232.279237
SSID	ssj0006209
Score	2.5122101
Snippet	In this paper, we present an FPGA based hardware accelerator '<inline-formula><tex-math notation="LaTeX"> \mathsf{HEPCloud}</tex-math> <inline-graphic... In this paper, we present an FPGA based hardware accelerator ‘[Formula Omitted]’ for homomorphic evaluations of medium depth functions which has applications...
SourceID	proquest crossref ieee
SourceType	Aggregation Database Enrichment Source Index Database Publisher
StartPage	1637
SubjectTerms	Acceleration Algorithms Cloud computing Computer architecture Computer memory Cybersecurity Encryption Feasibility studies Field programmable gate arrays Hardware hardware implementation Homomorphic encryption lattice-based cryptography Microprocessors number theoretic transform Parallel processing Parameters Pipelining (computers) polynomial multiplication Polynomials ring-LWE Rings (mathematics)
Title	HEPCloud: An FPGA-Based Multicore Processor for FV Somewhat Homomorphic Function Evaluation
URI	https://ieeexplore.ieee.org/document/8318681 https://www.proquest.com/docview/2117182718
Volume	67
WOSCitedRecordID	wos000446704900010&url=https%3A%2F%2Fcvtisr.summon.serialssolutions.com%2F%23%21%2Fsearch%3Fho%3Df%26include.ft.matches%3Dt%26l%3Dnull%26q%3D
hasFullText	1
inHoldings	1
isFullTextHit
isPrint
journalDatabaseRights	– providerCode: PRVIEE databaseName: IEEE Electronic Library (IEL) customDbUrl: eissn: 1557-9956 dateEnd: 99991231 omitProxy: false ssIdentifier: ssj0006209 issn: 0018-9340 databaseCode: RIE dateStart: 19680101 isFulltext: true titleUrlDefault: https://ieeexplore.ieee.org/ providerName: IEEE
link	http://cvtisr.summon.serialssolutions.com/2.0.0/link/0/eLvHCXMwlV3NS-wwEB9UPDwPfj5x_SIHDx7s2m3SJPW2Llv3ILLgKsI7lHxMUdCtrLv675t0s0V4epBQ6CEJJb9OZiaZ-Q3AiWWJlrHhUSoTGzGm00hhKSPZSbWwPiqA14nC1-LmRj48ZMMlOGtyYRCxDj7Dtn-t7_JtZWb-qOxcUk_u7nydZSH4PFer2XX5Ipyj4wSYsjjQ-HTi7HzU8yFcsp34OzJ_yvFFA9UlVf7bh2vlkm_87rM2YT0YkaQ7R30LlnC8DRuLAg0kyOs2rH1hG9yBf4P-sPdczewF6Y5JPrzqRpdOh1lSJ-F6OksS0gaqCXG2LMnvyW31gh-PakoG1YtrDpQnQ3KnCz2epN9Qhf-Fu7w_6g2iUFshMpTG06h0oq2cvlbePmRKoNWZFkhjpV0HlDw2mndMJkotjGtWW8pVnKaJQeZmoLuwMq7GuAeEi5KlSnjquIxRxSWnHDlDt3EmiGnZgvZivQsTiMd9_YvnonZA4qwY9QoPUBEAasFpM-B1zrnxc9cdj0fTLUDRgsMFoEWQybfCubpOESfu2f9-1AH88XPPMw0PYWU6meERrJr36dPb5Lj-3T4Bcs_RAg
linkProvider	IEEE
linkToHtml	http://cvtisr.summon.serialssolutions.com/2.0.0/link/0/eLvHCXMwlV3NT9swFH9CMGnsABswrawMH3bYYSlu7DgOt1I1K1pXVVpBSBwif7xoSNCgfmz__uzUjZBgh8mKlIOdWPnlfdh-7_cAPlsea0mNiBIZ24hznUQKSxnJbqJT66MCRJ0oPErHY3lzk0224GuTC4OIdfAZdvxtfZZvK7PyW2Vnknlyd7fW2Uk4j-k6W6vRu2IT0NF1Isw4DUQ-XZqdTfs-iEt2Yn9K5vc5ntiguqjKM01cm5d8__8m9hb2ghtJemvc38EWzg5gf1OigQSJPYA3T_gGD-F2OJj076uVPSe9Gckn33rRhbNiltRpuJ7QkoTEgWpOnDdL8mvys3rAP7_UkgyrB9ccLHeG5M4aekTJoCELP4KrfDDtD6NQXSEyjNFlVDrhVs5iK-8hcpWi1ZlOkVGlXQeUghotuiZLS50a16y2TCiaJLFB7p7A3sP2rJrhByAiLXmiUk8el3GmhBRMoODoVGeMmJQt6Gy-d2EC9bivgHFf1EsQmhXTfuEBKgJALfjSDHhcs278u-uhx6PpFqBoQXsDaBGkclG4xa4zxbG7jl8edQqvh9Mfo2J0Of7-EXb9e9Z5h23YXs5XeAKvzO_l3WL-qf71_gJ7sdRJ
openUrl	ctx_ver=Z39.88-2004&ctx_enc=info%3Aofi%2Fenc%3AUTF-8&rfr_id=info%3Asid%2Fsummon.serialssolutions.com&rft_val_fmt=info%3Aofi%2Ffmt%3Akev%3Amtx%3Ajournal&rft.genre=article&rft.atitle=HEPCloud%3A+An+FPGA-based+Multicore+Processor+for+FV+Somewhat+Homomorphic+Function+Evaluation&rft.jtitle=IEEE+transactions+on+computers&rft.au=Sinha+Roy%2C+Sujoy&rft.au=Jarvinen%2C+Kimmo&rft.au=Vliegen%2C+Jo&rft.au=Vercauteren%2C+Frederik&rft.date=2018-11-01&rft.issn=0018-9340&rft.spage=1&rft.epage=1&rft_id=info:doi/10.1109%2FTC.2018.2816640&rft.externalDBID=n%2Fa&rft.externalDocID=10_1109_TC_2018_2816640
thumbnail_l	http://covers-cdn.summon.serialssolutions.com/index.aspx?isbn=/lc.gif&issn=0018-9340&client=summon
thumbnail_m	http://covers-cdn.summon.serialssolutions.com/index.aspx?isbn=/mc.gif&issn=0018-9340&client=summon
thumbnail_s	http://covers-cdn.summon.serialssolutions.com/index.aspx?isbn=/sc.gif&issn=0018-9340&client=summon