Low-Complexity Image and Video Coding Based on an Approximate Discrete Tchebichef Transform

The usage of linear transformations has great relevance for data decorrelation applications, like image and video compression. In that sense, the discrete Tchebichef transform (DTT) possesses useful coding and decorrelation properties. The DTT transform kernel does not depend on the input data and f...

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Vydáno v:IEEE transactions on circuits and systems for video technology Ročník 27; číslo 5; s. 1066 - 1076
Hlavní autoři: Oliveira, Paulo A. M., Cintra, Renato J., Bayer, Fabio M., Kulasekera, Sunera, Madanayake, Arjuna
Médium: Journal Article
Jazyk:angličtina
Vydáno: New York IEEE 01.05.2017
The Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Institute of Electrical and Electronics Engineers
Témata:
Algorithms
Approximate transforms
Approximation algorithms
Approximation methods
Complexity
Complexity theory
Computer Arithmetic
Computer Science
Computer simulation
Discrete cosine transforms
discrete Tchebichef transform (DTT)
Embedded Systems
Engineering Sciences
fast algorithms
Hardware Architecture
image and video coding
Image coding
Image compression
Linear transformations
Reduction
Signal and Image processing
Video coding
Video compression
ISSN:1051-8215, 1558-2205
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Popis
Shrnutí:The usage of linear transformations has great relevance for data decorrelation applications, like image and video compression. In that sense, the discrete Tchebichef transform (DTT) possesses useful coding and decorrelation properties. The DTT transform kernel does not depend on the input data and fast algorithms can be developed to real-time applications. However, the DTT fast algorithm presented in literature possess high computational complexity. In this paper, we introduce a new low-complexity approximation for the DTT. The fast algorithm of the proposed transform is multiplication free and requires a reduced number of additions and bit-shifting operations. Image and video compression simulations in popular standards show good performance of the proposed transform. Regarding hardware resource consumption for FPGA shows a 43.1% reduction in configurable logic blocks and ASIC place and route realization shows a 57.7% reduction in the area-time figure compared with the 2D version of the exact DTT.
Bibliografie:ObjectType-Article-1
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ISSN:1051-8215
1558-2205
DOI:10.1109/TCSVT.2016.2515378