High-throughput partial-parallel block-layered decoding architecture for nonbinary LDPC codes

This paper presents a novel forward-backward four-way merger min-max algorithm and high-throughput decoder architecture for nonbinary low-density parity-check (NB-LDPC) decoding, which significantly reduces decoding latency. An efficient partial-parallel block-layered decoder architecture suitable f...

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Veröffentlicht in:Integration (Amsterdam) Jg. 59; S. 52 - 63
Hauptverfasser: Pham Thi, Huyen, Ajaz, Sabooh, Lee, Hanho
Format: Journal Article
Sprache:Englisch
Veröffentlicht: Amsterdam Elsevier B.V 01.09.2017
Elsevier BV
Schlagworte:
Algorithms
Block-layered decoding
Chemical synthesis
CMOS
Decoding
Error correcting codes
Iterative decoding
Min–max
Nonbinary LDPC
Studies
Nonbinary LDPC
Block-layered decoding
Min–max
Iterative decoding
ISSN:0167-9260, 1872-7522
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Zusammenfassung:This paper presents a novel forward-backward four-way merger min-max algorithm and high-throughput decoder architecture for nonbinary low-density parity-check (NB-LDPC) decoding, which significantly reduces decoding latency. An efficient partial-parallel block-layered decoder architecture suitable for the proposed forward-backward four-way merger algorithm is presented to speed up the decoder convergence. Moreover, a parallel switch network architecture and parallel-serial check node unit are also proposed to facilitate the implementation of the proposed decoder architecture. The proposed algorithm can reduce the number of check node processing steps by half. Consequently, the decoder architecture using the proposed algorithm can achieve a considerably higher throughput, compared to previous works. Two quasi-cyclic NB-LDPC (QC-NB-LDPC) codes over GF(32) as (837, 726) and (744, 653) are synthesized using a 90-nm CMOS technology. The implementation results demonstrate that the proposed decoder architecture can operate at a 370MHz clock frequency, and the throughputs of these two codes are 92.6 Mbps and 118.86 Mbps, respectively. •A novel forward-backward four-way merger min-max (FB4M-MM) algorithm is proposed.•A parallel ECU architecture for CNU is proposed.•Proposed PS-ECU architecture reduces CNU latency by half, and significantly improves throughput.•The partial-parallel block-layered decoder using the FB4M-MM algorithm has a high throughput and low hardware complexity.•The decoder has higher efficiency compared to conventional decoders.
Bibliographie:ObjectType-Article-1
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ISSN:0167-9260
1872-7522
DOI:10.1016/j.vlsi.2017.05.005