High-throughput partial-parallel block-layered decoding architecture for nonbinary LDPC codes
This paper presents a novel forward-backward four-way merger min-max algorithm and high-throughput decoder architecture for nonbinary low-density parity-check (NB-LDPC) decoding, which significantly reduces decoding latency. An efficient partial-parallel block-layered decoder architecture suitable f...
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| Abstract | This paper presents a novel forward-backward four-way merger min-max algorithm and high-throughput decoder architecture for nonbinary low-density parity-check (NB-LDPC) decoding, which significantly reduces decoding latency. An efficient partial-parallel block-layered decoder architecture suitable for the proposed forward-backward four-way merger algorithm is presented to speed up the decoder convergence. Moreover, a parallel switch network architecture and parallel-serial check node unit are also proposed to facilitate the implementation of the proposed decoder architecture. The proposed algorithm can reduce the number of check node processing steps by half. Consequently, the decoder architecture using the proposed algorithm can achieve a considerably higher throughput, compared to previous works. Two quasi-cyclic NB-LDPC (QC-NB-LDPC) codes over GF(32) as (837, 726) and (744, 653) are synthesized using a 90-nm CMOS technology. The implementation results demonstrate that the proposed decoder architecture can operate at a 370MHz clock frequency, and the throughputs of these two codes are 92.6 Mbps and 118.86 Mbps, respectively.
•A novel forward-backward four-way merger min-max (FB4M-MM) algorithm is proposed.•A parallel ECU architecture for CNU is proposed.•Proposed PS-ECU architecture reduces CNU latency by half, and significantly improves throughput.•The partial-parallel block-layered decoder using the FB4M-MM algorithm has a high throughput and low hardware complexity.•The decoder has higher efficiency compared to conventional decoders. |
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| AbstractList | This paper presents a novel forward-backward four-way merger min-max algorithm and high-throughput decoder architecture for nonbinary low-density parity-check (NB-LDPC) decoding, which significantly reduces decoding latency. An efficient partial-parallel block-layered decoder architecture suitable for the proposed forward-backward four-way merger algorithm is presented to speed up the decoder convergence. Moreover, a parallel switch network architecture and parallel-serial check node unit are also proposed to facilitate the implementation of the proposed decoder architecture. The proposed algorithm can reduce the number of check node processing steps by half. Consequently, the decoder architecture using the proposed algorithm can achieve a considerably higher throughput, compared to previous works. Two quasi-cyclic NB-LDPC (QC-NB-LDPC) codes over GF(32) as (837, 726) and (744, 653) are synthesized using a 90-nm CMOS technology. The implementation results demonstrate that the proposed decoder architecture can operate at a 370 MHz clock frequency, and the throughputs of these two codes are 92.6 Mbps and 118.86 Mbps, respectively. This paper presents a novel forward-backward four-way merger min-max algorithm and high-throughput decoder architecture for nonbinary low-density parity-check (NB-LDPC) decoding, which significantly reduces decoding latency. An efficient partial-parallel block-layered decoder architecture suitable for the proposed forward-backward four-way merger algorithm is presented to speed up the decoder convergence. Moreover, a parallel switch network architecture and parallel-serial check node unit are also proposed to facilitate the implementation of the proposed decoder architecture. The proposed algorithm can reduce the number of check node processing steps by half. Consequently, the decoder architecture using the proposed algorithm can achieve a considerably higher throughput, compared to previous works. Two quasi-cyclic NB-LDPC (QC-NB-LDPC) codes over GF(32) as (837, 726) and (744, 653) are synthesized using a 90-nm CMOS technology. The implementation results demonstrate that the proposed decoder architecture can operate at a 370MHz clock frequency, and the throughputs of these two codes are 92.6 Mbps and 118.86 Mbps, respectively. •A novel forward-backward four-way merger min-max (FB4M-MM) algorithm is proposed.•A parallel ECU architecture for CNU is proposed.•Proposed PS-ECU architecture reduces CNU latency by half, and significantly improves throughput.•The partial-parallel block-layered decoder using the FB4M-MM algorithm has a high throughput and low hardware complexity.•The decoder has higher efficiency compared to conventional decoders. |
| Author | Lee, Hanho Ajaz, Sabooh Pham Thi, Huyen |
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| Cites_doi | 10.1109/TVLSI.2013.2293224 10.1109/TVLSI.2010.2047956 10.1109/TCOMM.2007.894088 10.1109/ISCAS.2014.6865152 10.1109/4234.681360 10.1049/el.2013.1673 10.1007/s11265-013-0864-x 10.1007/s11265-013-0816-5 10.1109/TSP.2013.2256905 10.1109/ISCAS.2015.7169065 10.1109/ISCAS.2014.6865151 10.1109/TMAG.2003.808600 10.1109/JSSC.2014.2362854 10.1109/ITW.2003.1216697 10.1109/ISOCC.2014.7087640 10.1109/ISIT.2008.4595169 10.1587/elex.11.20130837 10.1109/ICC.2004.1312606 10.1109/TVLSI.2012.2218839 10.1109/TIT.1962.1057683 10.1109/TCOMM.2008.060527 10.1109/ISIT.2008.4595129 10.1109/TVLSI.2012.2210452 10.1109/LES.2014.2311317 |
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| Keywords | Nonbinary LDPC Block-layered decoding Min–max Iterative decoding |
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| SubjectTerms | Algorithms Block-layered decoding Chemical synthesis CMOS Decoding Error correcting codes Iterative decoding Min–max Nonbinary LDPC Studies |
| Title | High-throughput partial-parallel block-layered decoding architecture for nonbinary LDPC codes |
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