Low-Area and High-Throughput Architecture for an Adaptive Filter Using Distributed Arithmetic

A high-performance implementation scheme for a least mean square adaptive filter is presented. The architecture is based on distributed arithmetic in which the partial products of filter coefficients are precomputed and stored in lookup tables (LUTs) and the filtering is done by shift-and-accumulate...

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Vydané v:IEEE transactions on circuits and systems. II, Express briefs Ročník 60; číslo 11; s. 781 - 785
Hlavní autori: Prakash, M. Surya, Shaik, Rafi Ahamed
Médium: Journal Article
Jazyk:English
Vydavateľské údaje: New York IEEE 01.11.2013
The Institute of Electrical and Electronics Engineers, Inc. (IEEE)
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Abstract A high-performance implementation scheme for a least mean square adaptive filter is presented. The architecture is based on distributed arithmetic in which the partial products of filter coefficients are precomputed and stored in lookup tables (LUTs) and the filtering is done by shift-and-accumulate operations on these partial products. In the case of an adaptive filter, it is required that the filter coefficients be updated and, hence, these LUTs are to be recalculated. A new strategy based on the offset binary coding scheme has been proposed in order to update these LUTs from time to time. Simulation results show that the proposed scheme consumes very less chip area and operates at high throughput for large base unit size k ( = N/m) , where m is an integer and N is the number of filter coefficients. For example, a 128-tap finite-impulse-response adaptive filter with the proposed implementation produces 12 times more throughput (for k = 8) and consumes almost 26% less area when compared to the best of existing architectures.
AbstractList A high-performance implementation scheme for a least mean square adaptive filter is presented. The architecture is based on distributed arithmetic in which the partial products of filter coefficients are precomputed and stored in lookup tables (LUTs) and the filtering is done by shift-and-accumulate operations on these partial products. In the case of an adaptive filter, it is required that the filter coefficients be updated and, hence, these LUTs are to be recalculated. A new strategy based on the offset binary coding scheme has been proposed in order to update these LUTs from time to time. Simulation results show that the proposed scheme consumes very less chip area and operates at high throughput for large base unit size syntax error at token } , where m is an integer and N is the number of filter coefficients. For example, a 128-tap finite-impulse-response adaptive filter with the proposed implementation produces 12 times more throughput (for k = 8 ) and consumes almost 26% less area when compared to the best of existing architectures.
A high-performance implementation scheme for a least mean square adaptive filter is presented. The architecture is based on distributed arithmetic in which the partial products of filter coefficients are precomputed and stored in lookup tables (LUTs) and the filtering is done by shift-and-accumulate operations on these partial products. In the case of an adaptive filter, it is required that the filter coefficients be updated and, hence, these LUTs are to be recalculated. A new strategy based on the offset binary coding scheme has been proposed in order to update these LUTs from time to time. Simulation results show that the proposed scheme consumes very less chip area and operates at high throughput for large base unit size [Formula Omitted], where [Formula Omitted] is an integer and [Formula Omitted] is the number of filter coefficients. For example, a 128-tap finite-impulse-response adaptive filter with the proposed implementation produces 12 times more throughput (for [Formula Omitted]) and consumes almost 26% less area when compared to the best of existing architectures.
A high-performance implementation scheme for a least mean square adaptive filter is presented. The architecture is based on distributed arithmetic in which the partial products of filter coefficients are precomputed and stored in lookup tables (LUTs) and the filtering is done by shift-and-accumulate operations on these partial products. In the case of an adaptive filter, it is required that the filter coefficients be updated and, hence, these LUTs are to be recalculated. A new strategy based on the offset binary coding scheme has been proposed in order to update these LUTs from time to time. Simulation results show that the proposed scheme consumes very less chip area and operates at high throughput for large base unit size k ( = N/m) , where m is an integer and N is the number of filter coefficients. For example, a 128-tap finite-impulse-response adaptive filter with the proposed implementation produces 12 times more throughput (for k = 8) and consumes almost 26% less area when compared to the best of existing architectures.
Author Prakash, M. Surya
Shaik, Rafi Ahamed
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Snippet A high-performance implementation scheme for a least mean square adaptive filter is presented. The architecture is based on distributed arithmetic in which the...
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SubjectTerms Adaptive filter
Adaptive filters
Architecture
Arithmetic
Clocks
Consumption
distributed arithmetic (DA)
Filtering
Filtration
finite impulse response (FIR)
Finite impulse response filters
least mean square (LMS)
Least mean squares algorithm
Least squares approximations
lookup table (LUT)
Lookup tables
offset binary coding (OBC)
Registers
Table lookup
Throughput
Title Low-Area and High-Throughput Architecture for an Adaptive Filter Using Distributed Arithmetic
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