A parallel Viterbi decoding algorithm

In this paper we express the Viterbi algorithm as a matrix–vector reduction in which multiplication is replaced by addition and addition by minimization. The resulting algorithm is then readily parallelized in a form suitable for implementation on a systolic processor array. We describe the algorith...

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Published in:Concurrency and computation Vol. 13; no. 2; pp. 95 - 102
Main Author: Reeve, J. S.
Format: Journal Article
Language:English
Published: Chichester, UK John Wiley & Sons, Ltd 01.02.2001
Subjects:
BCH codes
trellis decoding
Viterbi decoding
ISSN:1532-0626, 1532-0634
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Abstract In this paper we express the Viterbi algorithm as a matrix–vector reduction in which multiplication is replaced by addition and addition by minimization. The resulting algorithm is then readily parallelized in a form suitable for implementation on a systolic processor array. We describe the algorithm for Bose–Chaudhuri–Hocquenghem (BCH) codes which have a task graph with its valence restricted to four inputs and four outputs. The method is also applicable to convolution codes, but the complexity of the task graph increases with the number of input bits for these codes. Results for BCH codes are given for two general purpose parallel machines, an IBM SP2 and a Meiko CS2. Copyright © 2001 John Wiley & Sons, Ltd.
AbstractList In this paper we express the Viterbi algorithm as a matrix-vector reduction in which multiplication is replaced by addition and addition by minimization. The resulting algorithm is then readily parallelized in a form suitable for implementation on a systolic processor array. We describe the algorithm for Bose-Chaudhuri-Hocquenghem (BCH) codes which have a task graph with its valence restricted to four inputs and four outputs. The method is also applicable to convolution codes, but the complexity of the task graph increases with the number of input bits for these codes. Results for BCH codes given for two general purpose parallel machines, an IBM SP2 and a Meiko CS2.
In this paper we express the Viterbi algorithm as a matrix–vector reduction in which multiplication is replaced by addition and addition by minimization. The resulting algorithm is then readily parallelized in a form suitable for implementation on a systolic processor array. We describe the algorithm for Bose–Chaudhuri–Hocquenghem (BCH) codes which have a task graph with its valence restricted to four inputs and four outputs. The method is also applicable to convolution codes, but the complexity of the task graph increases with the number of input bits for these codes. Results for BCH codes are given for two general purpose parallel machines, an IBM SP2 and a Meiko CS2. Copyright © 2001 John Wiley & Sons, Ltd.
Author Reeve, J. S.
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10.1016/S0165-1684(99)00176-0
10.1109/4.845186
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10.1109/30.793540
10.1145/367766.368168
10.1016/S0019-9958(60)90287-4
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  doi: 10.1109/TIT.1967.1054010
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Snippet In this paper we express the Viterbi algorithm as a matrix–vector reduction in which multiplication is replaced by addition and addition by minimization. The...
In this paper we express the Viterbi algorithm as a matrix-vector reduction in which multiplication is replaced by addition and addition by minimization. The...
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SubjectTerms BCH codes
trellis decoding
Viterbi decoding
Title A parallel Viterbi decoding algorithm
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