MeshWorks: A Comprehensive Framework for Optimized Clock Mesh Network Synthesis

Clock mesh networks are well known for their variation tolerance. But their usage is limited to high-end designs due to the significantly high resource requirements compared to clock trees and the lack of automatic mesh synthesis tools. Most existing works on clock mesh networks either deal with sem...

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Veröffentlicht in:IEEE transactions on computer-aided design of integrated circuits and systems Jg. 29; H. 12; S. 1945 - 1958
Hauptverfasser: Rajaram, Anand, Pan, David Z
Format: Journal Article
Sprache:Englisch
Veröffentlicht: New York IEEE 01.12.2010
The Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Schlagworte:
Algorithm design and analysis
Blocking
Clock mesh optimization
clock mesh synthesis
Clocks
Clocks & watches
Design engineering
Electromigration
Mesh networks
Network synthesis
Networks
Optimization
Planning
robust clock networks
Studies
Synthesis
Tolerances
variation tolerant clock network synthesis
Wireless networks
ISSN:0278-0070, 1937-4151
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Zusammenfassung:Clock mesh networks are well known for their variation tolerance. But their usage is limited to high-end designs due to the significantly high resource requirements compared to clock trees and the lack of automatic mesh synthesis tools. Most existing works on clock mesh networks either deal with semi-custom design or perform optimizations on a given clock mesh. However, the problem of obtaining a good initial clock mesh has not been addressed. Also, the problem of achieving a smooth tradeoff between variation tolerance and resource requirements has not been addressed adequately. In this paper, we present our MeshWorks framework, the first comprehensive automated framework for planning, synthesis, and optimization of clock mesh networks that addresses the above issues. Experimental results suggest that our algorithms can achieve an additional reduction of 31% in buffer area, 21% in wirelength, and 23% in power, compared to the best previous work, with similar worst case maximum frequency. We also demonstrate the effectiveness of our framework under several practical issues such as blockages, multiple clocks, uneven load distribution, and electromigration violations.
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ISSN:0278-0070
1937-4151
DOI:10.1109/TCAD.2010.2061130