Design and Implementation of a Real-Time Image Processing System Based on Sobel Edge Detection using Model-based Design Methods

Image processing and computer vision applications often use the Sobel edge detection technique in order to discover corners in input photographs. This is done in order to improve accuracy and efficiency. For the great majority of today's image processing applications, real-time implementation o...

Full description

Saved in:
Bibliographic Details
Published in:International journal of advanced computer science & applications Vol. 15; no. 3
Main Authors: Saidani, Taoufik, Ghodhbani, Refka, Ammar, Mohamed Ben, Kouki, Marouan, Algarni, Mohammad H, Said, Yahia, Kachoukh, Amani, Alsuwaylimi, Amjad A., Maqbool, Albia, Abd-Elkawy, Eman H.
Format: Journal Article
Language:English
Published: West Yorkshire Science and Information (SAI) Organization Limited 2024
Subjects:
Computer vision
Edge detection
Field programmable gate arrays
Hardware description languages
High level synthesis
Image processing
Real time
Video data
ISSN:2158-107X, 2156-5570
Online Access:Get full text
Tags: Add Tag
No Tags, Be the first to tag this record!
Description
Summary:Image processing and computer vision applications often use the Sobel edge detection technique in order to discover corners in input photographs. This is done in order to improve accuracy and efficiency. For the great majority of today's image processing applications, real-time implementation of image processing techniques like Sobel edge detection in hardware devices like field-programmable gate arrays (FPGAs) is required. Sobel edge detection is only one example. The use of FPGAs makes it feasible to have a quicker algorithmic throughput, which is required in order to match real-time speeds or in circumstances when it is critical to have faster data rates. The results of this study allowed for the Sobel edge detection approach to be applied in a manner that was not only speedy but also space-efficient. For the purpose of actually putting the recommended implementation into action, a one-of-a-kind high-level synthesis (HLS) design approach for intermediate data nodes that is based on application-specific bit widths was used. The high-level simulation code known as register transfer level (RTL) was generated by using the MATLAB HDL coder for HLS. The code written in hardware description language (HDL) that was produced was implemented on a Xilinx ZedBoard with the aid of the Vivado software, and it was tested in real time with the assistance of an input video stream.
Bibliography:ObjectType-Article-1
SourceType-Scholarly Journals-1
ObjectType-Feature-2
content type line 14
ISSN:2158-107X
2156-5570
DOI:10.14569/IJACSA.2024.0150328