A Low Overhead High Test Compression Technique Using Pattern Clustering With n-Detection Test Support

This paper presents a test data compression scheme that can be used to further improve compressions achieved by linear-feedback shift register (LFSR) reseeding. The proposed compression technique can be implemented with very low hardware overhead. The test data to be stored in the automatic test equ...

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Vydané v:	IEEE transactions on very large scale integration (VLSI) systems Ročník 18; číslo 12; s. 1672 - 1685
Hlavní autori:	Wang, Seongmoon, Wei, Wenlong, Wang, Zhanglei
Médium:	Journal Article
Jazyk:	English
Vydavateľské údaje:	New York, NY IEEE 01.12.2010 Institute of Electrical and Electronics Engineers The Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Predmet:	Applied sciences Automatic test equipment Automatic testing Circuit faults Circuit properties Circuit testing Digital circuits Electric, optical and optoelectronic circuits Electronic circuits Electronics Exact sciences and technology Hardware Image coding linear decompression Linear-feedback shift register (LFSR) reseeding n-detection testing Pattern clustering Shift registers Studies Test data compression Test pattern generators Test systems Testing, measurement, noise and reliability test data compression linear decompression Data compression Feedback regulation Compact design Automatic test Linear-feedback shift register (LFSR) reseeding Stuck at fault Aggregation Shift register n-detection testing Testing equipment Deterministic approach
ISSN:	1063-8210, 1557-9999
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Abstract	This paper presents a test data compression scheme that can be used to further improve compressions achieved by linear-feedback shift register (LFSR) reseeding. The proposed compression technique can be implemented with very low hardware overhead. The test data to be stored in the automatic test equipment (ATE) memory are much smaller than that for previously published schemes, and the number of test patterns that need to be generated is smaller than other weighted random pattern testing schemes. The proposed technique can be extended to generate test patterns that achieve high n-detection fault coverage. This technique compresses a regular 1-detection test cube set instead of an n-detection test cube set, which is typically n times larger. Hence, the volume of compressed test data for n-detection test is comparable to that for 1-detection test. Experimental results on a large industry design show that over 1600X compression is achievable by the proposed scheme with the test sequence length, which is comparable to that of highly compacted deterministic patterns. Experimental results on n -detection test show that test patterns generated by the proposed decompressor can achieve very high 5-detection stuck-at fault coverage and high compression for large benchmark circuits.
AbstractList	This paper presents a test data compression scheme that can be used to further improve compressions achieved by linear-feedback shift register (LFSR) reseeding. The proposed compression technique can be implemented with very low hardware overhead. The test data to be stored in the automatic test equipment (ATE) memory are much smaller than that for previously published schemes, and the number of test patterns that need to be generated is smaller than other weighted random pattern testing schemes. The proposed technique can be extended to generate test patterns that achieve high $n$-detection fault coverage. This technique compresses a regular 1-detection test cube set instead of an $n$-detection test cube set, which is typically $n$ times larger. Hence, the volume of compressed test data for $n$-detection test is comparable to that for 1-detection test. Experimental results on a large industry design show that over 1600X compression is achievable by the proposed scheme with the test sequence length, which is comparable to that of highly compacted deterministic patterns. Experimental results on $n$ -detection test show that test patterns generated by the proposed decompressor can achieve very high 5-detection stuck-at fault coverage and high compression for large benchmark circuits.
Author	Seongmoon Wang Zhanglei Wang Wenlong Wei
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Keywords	test data compression linear decompression Data compression Feedback regulation Compact design Automatic test Linear-feedback shift register (LFSR) reseeding Stuck at fault Aggregation Shift register n-detection testing Testing equipment Deterministic approach
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SubjectTerms	Applied sciences Automatic test equipment Automatic testing Circuit faults Circuit properties Circuit testing Digital circuits Electric, optical and optoelectronic circuits Electronic circuits Electronics Exact sciences and technology Hardware Image coding linear decompression Linear-feedback shift register (LFSR) reseeding n-detection testing Pattern clustering Shift registers Studies Test data compression Test pattern generators Test systems Testing, measurement, noise and reliability
Title	A Low Overhead High Test Compression Technique Using Pattern Clustering With n-Detection Test Support
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