Approximate Multipliers Using Bio-Inspired Algorithm

As most of the real-world problems are imprecise, dedicating a lot of hardware for precise computations is futile for low-power applications and few applications where the precision is not of paramount importance. For such applications an imprecise computational block is sufficient if it has other p...

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Vydané v:Journal of electrical engineering & technology Ročník 16; číslo 1; s. 559 - 568
Hlavní autori: Senthilkumar, K. K., Kumarasamy, Kunaraj, Dhandapani, Vaithiyanathan
Médium: Journal Article
Jazyk:English
Vydavateľské údaje: Singapore Springer Singapore 01.01.2021
대한전기학회
Predmet:
Electrical Engineering
Electrical Machines and Networks
Electronics and Microelectronics
Engineering
Instrumentation
Original Article
Power Electronics
전기공학
Imprecise computation
Low power arithmetic
Cartesian Genetic Programming
Recursive multiplier
Evolutionary computation
ISSN:1975-0102, 2093-7423
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Popis
Shrnutí:As most of the real-world problems are imprecise, dedicating a lot of hardware for precise computations is futile for low-power applications and few applications where the precision is not of paramount importance. For such applications an imprecise computational block is sufficient if it has other performance benefits like low power and low area. We propose Constrained Cartesian Genetic Programming (CCGP), a variant of CGP to evolve lower order imprecise multipliers and further the higher order multipliers are constructed from them. Gate-level architectures for 2 × 2, 3 × 2, 3 × 3 and 4 × 4 imprecise multipliers are evolved. Also, we propose few partitioning methodologies for the construction of higher order multipliers using the evolved imprecise lower order multipliers. The constructed evolved-partitioned multiplier (EPM) of orders 8 × 8 and 16 × 16 has significant performance benefits over the existing multiplier architectures in terms of cell area and power. The circuits are synthesized using Cadence SoC Encounter ® using TSMC ® 180 nm standard cell library. The 16-bit EPMs show a maximum power reduction of 33% compared to other truncated multipliers and an area improvement of 2%.
ISSN:1975-0102
2093-7423
DOI:10.1007/s42835-020-00564-w